rename southbridge i440bx to its actual name i8371eb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -9,7 +9,7 @@
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
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#include "southbridge/intel/i8371eb/i8371eb_early_smbus.c"
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#include "superio/NSC/pc87351/pc87351_early_serial.c"
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#include "northbridge/intel/i440bx/raminit.h"
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#include "cpu/x86/mtrr/earlymtrr.c"
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@ -1,13 +0,0 @@
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#ifndef I440BX_CHIP_H
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#define I440BX_CHIP_H
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struct southbridge_intel_i440bx_config
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{
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unsigned int ide0_enable : 1;
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unsigned int ide1_enable : 1;
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};
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struct chip_operations;
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extern struct chip_operations southbridge_intel_i440bx_ops;
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#endif /* I440BX_CHIP_H */
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@ -0,0 +1,13 @@
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#ifndef I8371EB_CHIP_H
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#define I8371EB_CHIP_H
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struct southbridge_intel_i8371eb_config
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{
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unsigned int ide0_enable : 1;
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unsigned int ide1_enable : 1;
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};
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struct chip_operations;
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extern struct chip_operations southbridge_intel_i8371eb_ops;
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#endif /* I8371EB_CHIP_H */
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@ -1,4 +1,4 @@
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#include "i440bx_smbus.h"
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#include "i8371eb_smbus.h"
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#define SMBUS_IO_BASE 0x0f00
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@ -10,7 +10,7 @@
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#include <device/pci_ops.h>
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#include <device/smbus.h>
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#include <arch/io.h>
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#include "i440bx.h"
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#include "i8371eb.h"
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static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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@ -31,7 +31,7 @@ static struct device_operations smbus_ops = {
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.enable_resources = pci_dev_enable_resources,
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.init = 0,
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.scan_bus = scan_static_bus,
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.enable = i440bx_enable,
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.enable = i8371eb_enable,
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.ops_pci = &lops_pci,
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.ops_smbus_bus = &lops_smbus_bus,
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};
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