soc/intel/skylake: Add support in SKL for PMC common code
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaunak Saha
Aaron Durbin
parent
f073872e22
commit
d347680995
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@ -65,6 +65,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_LPC
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCIE
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select SOC_INTEL_COMMON_BLOCK_PMC
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SA
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@ -23,6 +23,7 @@
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/smbus.h>
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#include <soc/bootblock.h>
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#include <soc/iomap.h>
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@ -130,4 +130,6 @@
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#define GPE0_LAN_WAK 112
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#define GPE0_WADT 114
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#define GPE_MAX GPE0_WADT
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#endif /* _SOC_GPE_H_ */
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@ -20,6 +20,8 @@
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#include <compiler.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <soc/gpe.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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/* ACPI_BASE_ADDRESS / PMBASE */
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@ -103,6 +105,7 @@
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#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
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#define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */
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#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
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#define GPE_STS_RSVD GPE_STD
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#define WADT_STS (1 << 18)
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#define LAN_WAK_STS (1 << 16)
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#define GPIO_T2_STS (1 << 15)
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@ -136,6 +139,13 @@
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */
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#define ETR 0xac
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# define CF9_LOCK (1 << 31)
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# define CF9_GLB_RST (1 << 20)
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#define PRSTS 0x10
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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@ -150,49 +160,26 @@ struct chipset_power_state {
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uint32_t prev_sleep_state;
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} __packed;
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/*
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* This is used only in FSP1_1 as we wanted to keep the flow unchanged.
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* Internally fill_power_state calls the new pmc_fill_power_state now
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*/
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#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
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struct chipset_power_state *fill_power_state(void);
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/* PM1_CNT */
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void enable_pm1_control(uint32_t mask);
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void disable_pm1_control(uint32_t mask);
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/* PM1 */
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uint16_t clear_pm1_status(void);
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void enable_pm1(uint16_t events);
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void update_pm1_enable(uint16_t events);
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uint16_t read_pm1_enable(void);
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uint32_t clear_smi_status(void);
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/* SMI */
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void enable_smi(uint32_t mask);
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void disable_smi(uint32_t mask);
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/* TCO */
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uint32_t clear_tco_status(void);
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void enable_tco_sci(void);
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/* GPE0 */
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uint32_t clear_gpe_status(void);
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void clear_gpe_enable(void);
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void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);
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void disable_all_gpe(void);
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void enable_gpe(uint32_t mask);
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void disable_gpe(uint32_t mask);
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#endif
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/* Return the selected ACPI SCI IRQ */
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int acpi_sci_irq(void);
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/* Get base address PMC memory mapped registers. */
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uint8_t *pmc_mmio_regs(void);
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/* Get base address of TCO I/O registers. */
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uint16_t smbus_tco_regs(void);
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/* Set the DISB after DRAM init */
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void pmc_set_disb(void);
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/* Initialize GPEs */
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void pmc_gpe_init(void);
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/* Return non-zero when RTC failure happened. */
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int rtc_failure(void);
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@ -91,11 +91,9 @@
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#define DSX_EN_LAN_WAKE_PIN (1 << 0)
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#define PMSYNC_TPR_CFG 0xc4
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#define PMSYNC_LOCK (1 << 31)
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#define GPIO_CFG 0x120
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#define GPIO_GPE_CFG 0x120
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#define GPE0_DWX_MASK 0xf
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#define GPE0_DW0_SHIFT 0
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#define GPE0_DW1_SHIFT 4
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#define GPE0_DW2_SHIFT 8
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#define GPE0_DW_SHIFT(x) (4*(x))
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#define GBLRST_CAUSE0 0x124
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#define GBLRST_CAUSE1 0x128
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#define CIR31C 0x31c
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@ -25,14 +25,15 @@
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#include <arch/acpi.h>
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#include <cpu/cpu.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/pmclib.h>
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#include <pc80/mc146818rtc.h>
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#include <reg_script.h>
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#include <string.h>
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#include <soc/gpio.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/pm.h>
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#include <soc/pmc.h>
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#include <cpu/x86/smm.h>
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#include <soc/pcr_ids.h>
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#include <soc/ramstage.h>
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@ -26,6 +26,7 @@
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <intelblocks/pmclib.h>
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#include <halt.h>
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#include <intelblocks/lpc_lib.h>
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#include <rules.h>
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@ -41,141 +42,13 @@
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#include <vboot/vbnv.h>
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#include "chip.h"
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/* Print status bits with descriptive names */
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static void print_status_bits(u32 status, const char * const bit_names[])
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{
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int i;
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if (!status)
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return;
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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/* Print status bits as GPIO numbers */
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static void print_gpio_status(u32 status, int start)
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{
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int i;
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if (!status)
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return;
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i))
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printk(BIOS_DEBUG, "GPIO%d ", start + i);
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}
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}
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/*
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* PM1_CNT
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*/
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/* Enable events in PM1 control register */
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void enable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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/* Disable events in PM1 control register */
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void disable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt &= ~mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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/*
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* PM1
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*/
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/* Clear and return PM1 status register */
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static u16 reset_pm1_status(void)
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{
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u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
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return pm1_sts;
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}
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/* Print PM1 status bits */
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static u16 print_pm1_status(u16 pm1_sts)
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{
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static const char * const pm1_sts_bits[] = {
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[0] = "TMROF",
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[4] = "BM",
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[5] = "GBL",
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[8] = "PWRBTN",
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[10] = "RTC",
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[11] = "PRBTNOR",
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[14] = "PCIEXPWAK",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_status_bits(pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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/* Print, clear, and return PM1 status */
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u16 clear_pm1_status(void)
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{
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return print_pm1_status(reset_pm1_status());
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}
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/* Set the PM1 register to events */
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void enable_pm1(u16 events)
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{
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outw(events, ACPI_BASE_ADDRESS + PM1_EN);
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}
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/*
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* Update supplied events in PM1_EN register. This does not disable any already
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* set events.
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*/
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void update_pm1_enable(u16 events)
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{
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u16 pm1_en = read_pm1_enable();
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pm1_en |= events;
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enable_pm1(pm1_en);
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}
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/* Read events set in PM1_EN register. */
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uint16_t read_pm1_enable(void)
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{
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return inw(ACPI_BASE_ADDRESS + PM1_EN);
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}
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/*
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* SMI
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*/
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/* Clear and return SMI status register */
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static u32 reset_smi_status(void)
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const char *const *soc_smi_sts_array(size_t *smi_arr)
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{
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u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
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outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
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return smi_sts;
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}
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/* Print SMI status bits */
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static u32 print_smi_status(u32 smi_sts)
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{
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static const char * const smi_sts_bits[] = {
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static const char *const smi_sts_bits[] = {
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[2] = "BIOS",
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[3] = "LEGACY_USB",
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[4] = "SLP_SMI",
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@ -199,70 +72,17 @@ static u32 print_smi_status(u32 smi_sts)
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[28] = "ESPI_SMI",
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_status_bits(smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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}
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/* Print, clear, and return SMI status */
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u32 clear_smi_status(void)
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{
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return print_smi_status(reset_smi_status());
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}
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/* Enable SMI event */
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void enable_smi(u32 mask)
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{
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u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en |= mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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}
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/* Disable SMI event */
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void disable_smi(u32 mask)
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{
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u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en &= ~mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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*smi_arr = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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/*
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* TCO
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*/
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/* Clear TCO status and return events that are enabled and active */
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static u32 reset_tco_status(void)
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const char *const *soc_tco_sts_array(size_t *tco_arr)
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{
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u16 tco1_sts;
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u16 tco2_sts;
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u16 tcobase;
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tcobase = smbus_tco_regs();
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/* TCO Status 2 register*/
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tco2_sts = inw(tcobase + TCO2_STS);
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tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
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outw(tco2_sts, tcobase + TCO2_STS);
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/* TCO Status 1 register*/
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tco1_sts = inw(tcobase + TCO1_STS);
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/* Clear SECOND_TO_STS bit */
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if (tco2_sts & TCO2_STS_SECOND_TO)
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outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
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return (tco2_sts << 16) | tco1_sts;
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}
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/* Print TCO status bits */
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static u32 print_tco_status(u32 tco_sts)
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{
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static const char * const tco_sts_bits[] = {
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI",
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[1] = "SW_TCO",
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[2] = "TCO_INT",
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@ -279,79 +99,17 @@ static u32 print_tco_status(u32 tco_sts)
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[20] = "SMLINK_SLV"
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
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print_status_bits(tco_sts, tco_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return tco_sts;
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*tco_arr = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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/* Print, clear, and return TCO status */
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u32 clear_tco_status(void)
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{
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return print_tco_status(reset_tco_status());
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}
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/* Enable TCO SCI */
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void enable_tco_sci(void)
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{
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/* Clear pending events */
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outl(TCOSCI_STS, ACPI_BASE_ADDRESS + GPE0_STS(3));
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/* Enable TCO SCI events */
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enable_gpe(TCOSCI_EN);
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}
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/*
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* GPE0
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*/
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/* Clear a GPE0 status and return events that are enabled and active */
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static u32 reset_gpe(u16 sts_reg, u16 en_reg)
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const char *const *soc_gpe_sts_array(size_t *gpe_arr)
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{
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u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);
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u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);
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outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg);
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/* Only report enabled events */
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return gpe0_sts & gpe0_en;
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}
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/* Print GPE0 status bits */
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static u32 print_gpe_status(u32 gpe0_sts, const char * const bit_names[])
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{
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if (!gpe0_sts)
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return 0;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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print_status_bits(gpe0_sts, bit_names);
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printk(BIOS_DEBUG, "\n");
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return gpe0_sts;
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}
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/* Print GPE0 GPIO status bits */
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static u32 print_gpe_gpio(u32 gpe0_sts, int start)
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{
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if (!gpe0_sts)
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return 0;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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print_gpio_status(gpe0_sts, start);
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printk(BIOS_DEBUG, "\n");
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return gpe0_sts;
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}
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/* Clear all GPE status and return "standard" GPE event status */
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u32 clear_gpe_status(void)
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{
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static const char * const gpe0_sts_3_bits[] = {
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static const char *const gpe_sts_bits[] = {
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[1] = "HOTPLUG",
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[2] = "SWGPE",
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[6] = "TCO_SCI",
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@ -367,72 +125,8 @@ u32 clear_gpe_status(void)
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[18] = "WADT"
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};
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print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
|
||||
print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
|
||||
print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64);
|
||||
return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
|
||||
gpe0_sts_3_bits);
|
||||
}
|
||||
|
||||
/* Read and clear GPE status (defined in arch/acpi.h) */
|
||||
int acpi_get_gpe(int gpe)
|
||||
{
|
||||
int bank;
|
||||
uint32_t mask, sts;
|
||||
struct stopwatch sw;
|
||||
int rc = 0;
|
||||
|
||||
if (gpe < 0 || gpe > GPE0_WADT)
|
||||
return -1;
|
||||
|
||||
bank = gpe / 32;
|
||||
mask = 1 << (gpe % 32);
|
||||
|
||||
/* Wait up to 1ms for GPE status to clear */
|
||||
stopwatch_init_msecs_expire(&sw, 1);
|
||||
do {
|
||||
if (stopwatch_expired(&sw))
|
||||
return rc;
|
||||
|
||||
sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
|
||||
if (sts & mask) {
|
||||
outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
|
||||
rc = 1;
|
||||
}
|
||||
} while (sts & mask);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Enable all requested GPE */
|
||||
void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
|
||||
{
|
||||
outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
|
||||
outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
|
||||
outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64));
|
||||
outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
|
||||
}
|
||||
|
||||
/* Disable all GPE */
|
||||
void disable_all_gpe(void)
|
||||
{
|
||||
enable_all_gpe(0, 0, 0, 0);
|
||||
}
|
||||
|
||||
/* Enable a standard GPE */
|
||||
void enable_gpe(u32 mask)
|
||||
{
|
||||
u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
|
||||
gpe0_en |= mask;
|
||||
outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
|
||||
}
|
||||
|
||||
/* Disable a standard GPE */
|
||||
void disable_gpe(u32 mask)
|
||||
{
|
||||
u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
|
||||
gpe0_en &= ~mask;
|
||||
outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
|
||||
*gpe_arr = ARRAY_SIZE(gpe_sts_bits);
|
||||
return gpe_sts_bits;
|
||||
}
|
||||
|
||||
int acpi_sci_irq(void)
|
||||
|
|
@ -472,7 +166,7 @@ uint8_t *pmc_mmio_regs(void)
|
|||
/* 4KiB alignment. */
|
||||
reg32 &= ~0xfff;
|
||||
|
||||
return (void *)(uintptr_t)reg32;
|
||||
return (void *)(uintptr_t) reg32;
|
||||
}
|
||||
|
||||
uint16_t smbus_tco_regs(void)
|
||||
|
|
@ -486,63 +180,49 @@ uint16_t smbus_tco_regs(void)
|
|||
return reg16;
|
||||
}
|
||||
|
||||
void poweroff(void)
|
||||
uint32_t soc_reset_tco_status(void)
|
||||
{
|
||||
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
|
||||
u16 tco1_sts;
|
||||
u16 tco2_sts;
|
||||
u16 tcobase;
|
||||
|
||||
/*
|
||||
* Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
|
||||
* to transition to S5 state. If halt is called in SMM, then it prevents
|
||||
* the SMI handler from being triggered and system never enters S5.
|
||||
*/
|
||||
if (!ENV_SMM)
|
||||
halt();
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
/* TCO Status 2 register */
|
||||
tco2_sts = inw(tcobase + TCO2_STS);
|
||||
tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
|
||||
outw(tco2_sts, tcobase + TCO2_STS);
|
||||
|
||||
/* TCO Status 1 register */
|
||||
tco1_sts = inw(tcobase + TCO1_STS);
|
||||
|
||||
/* Clear SECOND_TO_STS bit */
|
||||
if (tco2_sts & TCO2_STS_SECOND_TO)
|
||||
outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
|
||||
|
||||
return (tco2_sts << 16) | tco1_sts;
|
||||
}
|
||||
|
||||
void pmc_gpe_init(void)
|
||||
uintptr_t soc_read_pmc_base(void)
|
||||
{
|
||||
return (uintptr_t) (pmc_mmio_regs());
|
||||
}
|
||||
|
||||
void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
|
||||
{
|
||||
DEVTREE_CONST struct soc_intel_skylake_config *config;
|
||||
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
|
||||
uint8_t *pmc_regs;
|
||||
uint32_t gpio_cfg;
|
||||
uint32_t gpio_cfg_reg;
|
||||
const uint32_t gpio_cfg_mask =
|
||||
(GPE0_DWX_MASK << GPE0_DW0_SHIFT) |
|
||||
(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
|
||||
(GPE0_DWX_MASK << GPE0_DW2_SHIFT);
|
||||
|
||||
/* Look up the device in devicetree */
|
||||
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
|
||||
if (!dev || !dev->chip_info) {
|
||||
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
|
||||
return;
|
||||
}
|
||||
config = dev->chip_info;
|
||||
pmc_regs = pmc_mmio_regs();
|
||||
|
||||
/* Route the GPIOs to the GPE0 block. Determine that all values
|
||||
* are different, and if they aren't use the reset values. */
|
||||
gpio_cfg = 0;
|
||||
if (config->gpe0_dw0 == config->gpe0_dw1 ||
|
||||
config->gpe0_dw1 == config->gpe0_dw2) {
|
||||
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
|
||||
gpio_cfg = read32(pmc_regs + GPIO_CFG);
|
||||
} else {
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;
|
||||
}
|
||||
gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;
|
||||
gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
|
||||
write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
|
||||
|
||||
/* Set the routes in the GPIO communities as well. */
|
||||
gpio_route_gpe((gpio_cfg_reg >> GPE0_DW0_SHIFT) & GPE0_DWX_MASK,
|
||||
(gpio_cfg_reg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK,
|
||||
(gpio_cfg_reg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK);
|
||||
|
||||
/* Set GPE enables based on devictree. */
|
||||
enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
|
||||
config->gpe0_en_3, config->gpe0_en_4);
|
||||
/* Assign to out variable */
|
||||
*dw0 = config->gpe0_dw0;
|
||||
*dw1 = config->gpe0_dw1;
|
||||
*dw2 = config->gpe0_dw2;
|
||||
}
|
||||
|
||||
int rtc_failure(void)
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <fsp/util.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <reset.h>
|
||||
#include <soc/me.h>
|
||||
#include <soc/pm.h>
|
||||
|
|
@ -22,19 +23,12 @@
|
|||
|
||||
static void do_force_global_reset(void)
|
||||
{
|
||||
u32 reg32;
|
||||
/*PMC Controller Device 0x1F, Func 02*/
|
||||
uint8_t *pmc_regs;
|
||||
|
||||
/*
|
||||
* BIOS should ensure it does a global reset
|
||||
* to reset both host and Intel ME by setting
|
||||
* PCH PMC [B0:D31:F2 register offset 0x1048 bit 20]
|
||||
*/
|
||||
pmc_regs = pmc_mmio_regs();
|
||||
reg32 = read32(pmc_regs + ETR3);
|
||||
reg32 |= ETR3_CF9GR;
|
||||
write32(pmc_regs + ETR3, reg32);
|
||||
pmc_global_reset_enable(true);
|
||||
|
||||
/* Now BIOS can write 0x06 or 0x0E to 0xCF9 port
|
||||
* to global reset platform */
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <arch/io.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
|
|
@ -27,63 +26,26 @@
|
|||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pmc.h>
|
||||
#include <soc/smbus.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/pmc.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <vboot/vboot_common.h>
|
||||
|
||||
static struct chipset_power_state power_state CAR_GLOBAL;
|
||||
|
||||
static struct chipset_power_state *get_power_state(void)
|
||||
{
|
||||
return car_get_var_ptr(&power_state);
|
||||
}
|
||||
|
||||
static void migrate_power_state(int is_recovery)
|
||||
{
|
||||
struct chipset_power_state *ps_cbmem;
|
||||
struct chipset_power_state *ps_car;
|
||||
|
||||
ps_car = get_power_state();
|
||||
ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
|
||||
|
||||
if (ps_cbmem == NULL) {
|
||||
printk(BIOS_DEBUG, "Not adding power state to cbmem!\n");
|
||||
return;
|
||||
}
|
||||
memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
|
||||
}
|
||||
ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
|
||||
#include <intelblocks/pmclib.h>
|
||||
|
||||
/* Return 0, 3, or 5 to indicate the previous sleep state. */
|
||||
static uint32_t prev_sleep_state(struct chipset_power_state *ps)
|
||||
int soc_prev_sleep_state(const struct chipset_power_state *ps,
|
||||
int prev_sleep_state)
|
||||
{
|
||||
/* Default to S0. */
|
||||
uint32_t prev_sleep_state = ACPI_S0;
|
||||
|
||||
if (ps->pm1_sts & WAK_STS) {
|
||||
switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
|
||||
case ACPI_S3:
|
||||
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
|
||||
prev_sleep_state = ACPI_S3;
|
||||
break;
|
||||
case ACPI_S5:
|
||||
prev_sleep_state = ACPI_S5;
|
||||
break;
|
||||
}
|
||||
/* Clear SLP_TYP. */
|
||||
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
} else {
|
||||
/*
|
||||
* Check for any power failure to determine if this a wake from
|
||||
* S5 because the PCH does not set the WAK_STS bit when waking
|
||||
* from a true G3 state.
|
||||
*/
|
||||
if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
|
||||
prev_sleep_state = ACPI_S5;
|
||||
}
|
||||
/*
|
||||
* Check for any power failure to determine if this a wake from
|
||||
* S5 because the PCH does not set the WAK_STS bit when waking
|
||||
* from a true G3 state.
|
||||
*/
|
||||
if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
|
||||
prev_sleep_state = ACPI_S5;
|
||||
|
||||
/*
|
||||
* If waking from S3 determine if deep S3 is enabled. If not,
|
||||
|
|
@ -101,57 +63,21 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
|
|||
if (ps->gen_pmcon_b & mask)
|
||||
prev_sleep_state = ACPI_S5;
|
||||
}
|
||||
|
||||
return prev_sleep_state;
|
||||
}
|
||||
|
||||
static void dump_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts);
|
||||
printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en);
|
||||
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt);
|
||||
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
|
||||
ps->tco1_sts, ps->tco2_sts);
|
||||
|
||||
printk(BIOS_DEBUG, "GPE0_STS: %08x %08x %08x %08x\n",
|
||||
ps->gpe0_sts[0], ps->gpe0_sts[1],
|
||||
ps->gpe0_sts[2], ps->gpe0_sts[3]);
|
||||
printk(BIOS_DEBUG, "GPE0_EN: %08x %08x %08x %08x\n",
|
||||
ps->gpe0_en[0], ps->gpe0_en[1],
|
||||
ps->gpe0_en[2], ps->gpe0_en[3]);
|
||||
|
||||
printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
|
||||
ps->gen_pmcon_a, ps->gen_pmcon_b);
|
||||
|
||||
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
|
||||
ps->gblrst_cause[0], ps->gblrst_cause[1]);
|
||||
|
||||
printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
|
||||
ps->prev_sleep_state);
|
||||
}
|
||||
|
||||
/* Fill power state structure from ACPI PM registers */
|
||||
struct chipset_power_state *fill_power_state(void)
|
||||
void soc_fill_power_state(struct chipset_power_state *ps)
|
||||
{
|
||||
uint16_t tcobase;
|
||||
uint8_t *pmc;
|
||||
struct chipset_power_state *ps = get_power_state();
|
||||
|
||||
tcobase = smbus_tco_regs();
|
||||
|
||||
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
|
||||
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
|
||||
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
ps->tco1_sts = inw(tcobase + TCO1_STS);
|
||||
ps->tco2_sts = inw(tcobase + TCO2_STS);
|
||||
ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
|
||||
ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
|
||||
ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
|
||||
ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
|
||||
ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
|
||||
ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
|
||||
ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
|
||||
ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
|
||||
|
||||
printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
|
||||
ps->tco1_sts, ps->tco2_sts);
|
||||
|
||||
ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
|
||||
ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B);
|
||||
|
|
@ -160,36 +86,17 @@ struct chipset_power_state *fill_power_state(void)
|
|||
ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
|
||||
ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
|
||||
|
||||
ps->prev_sleep_state = prev_sleep_state(ps);
|
||||
printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
|
||||
ps->gen_pmcon_a, ps->gen_pmcon_b);
|
||||
|
||||
dump_power_state(ps);
|
||||
|
||||
return ps;
|
||||
printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
|
||||
ps->gblrst_cause[0], ps->gblrst_cause[1]);
|
||||
}
|
||||
|
||||
int acpi_get_sleep_type(void)
|
||||
{
|
||||
struct chipset_power_state *ps;
|
||||
|
||||
ps = get_power_state();
|
||||
ps = pmc_get_power_state();
|
||||
return ps->prev_sleep_state;
|
||||
}
|
||||
|
||||
int vboot_platform_is_resuming(void)
|
||||
{
|
||||
return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
|
||||
}
|
||||
|
||||
/*
|
||||
* The PM1 control is set to S5 when vboot requests a reboot because the power
|
||||
* state code above may not have collected it's data yet. Therefore, set it to
|
||||
* S5 when vboot requests a reboot. That's necessary if vboot fails in the
|
||||
* resume path and requests a reboot. This prevents a reboot loop where the
|
||||
* error is continually hit on the failing vboot resume path.
|
||||
*/
|
||||
void vboot_platform_prepare_reboot(void)
|
||||
{
|
||||
uint16_t port = ACPI_BASE_ADDRESS + PM1_CNT;
|
||||
|
||||
outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <device/pci_def.h>
|
||||
#include <elog.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <reset.h>
|
||||
#include <romstage_handoff.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
|
@ -256,3 +257,13 @@ void soc_after_ram_init(struct romstage_params *params)
|
|||
*/
|
||||
pmc_set_disb();
|
||||
}
|
||||
|
||||
struct chipset_power_state *fill_power_state(void)
|
||||
{
|
||||
struct chipset_power_state *ps;
|
||||
|
||||
ps = pmc_get_power_state();
|
||||
pmc_fill_power_state(ps);
|
||||
|
||||
return ps;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@
|
|||
#include <device/pci_def.h>
|
||||
#include <fsp/util.h>
|
||||
#include <fsp/memmap.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <memory_info.h>
|
||||
#include <soc/intel/common/smbios.h>
|
||||
#include <soc/msr.h>
|
||||
|
|
@ -119,9 +120,9 @@ asmlinkage void car_stage_entry(void)
|
|||
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
|
||||
systemagent_early_init();
|
||||
|
||||
ps = fill_power_state();
|
||||
ps = pmc_get_power_state();
|
||||
timestamp_add_now(TS_START_ROMSTAGE);
|
||||
s3wake = ps->prev_sleep_state == ACPI_S3;
|
||||
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
|
||||
fsp_memory_init(s3wake);
|
||||
pmc_set_disb();
|
||||
if (!s3wake)
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <cpu/cpu.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <string.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pch.h>
|
||||
|
|
@ -45,18 +46,18 @@ void southbridge_smm_clear_state(void)
|
|||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
/* Dump and clear status registers */
|
||||
clear_smi_status();
|
||||
clear_pm1_status();
|
||||
clear_tco_status();
|
||||
clear_gpe_status();
|
||||
pmc_clear_smi_status();
|
||||
pmc_clear_pm1_status();
|
||||
pmc_clear_tco_status();
|
||||
pmc_clear_gpe_status();
|
||||
}
|
||||
|
||||
void southbridge_smm_enable_smi(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Enabling SMIs.\n");
|
||||
/* Configure events */
|
||||
enable_pm1(GBL_EN);
|
||||
disable_gpe(PME_B0_EN);
|
||||
pmc_enable_pm1(GBL_EN);
|
||||
pmc_disable_gpe(PME_B0_EN);
|
||||
|
||||
/*
|
||||
* Enable SMI generation:
|
||||
|
|
@ -68,7 +69,7 @@ void southbridge_smm_enable_smi(void)
|
|||
* - on microcontroller writes (io 0x62/0x66)
|
||||
* - on TCO events
|
||||
*/
|
||||
enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
|
||||
pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS);
|
||||
}
|
||||
|
||||
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
|
||||
|
|
@ -100,7 +101,7 @@ static void pm1_enable_pwrbtn_smi(void *unused)
|
|||
* any shutdowns because of power button presses due to power button
|
||||
* press in resume path.
|
||||
*/
|
||||
update_pm1_enable(PWRBTN_EN);
|
||||
pmc_update_pm1_enable(PWRBTN_EN);
|
||||
}
|
||||
|
||||
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <intelblocks/uart.h>
|
||||
#include <intelblocks/pmclib.h>
|
||||
#include <delay.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <elog.h>
|
||||
|
|
@ -81,7 +82,7 @@ int southbridge_io_trap_handler(int smif)
|
|||
/* Set the EOS bit */
|
||||
void southbridge_smi_set_eos(void)
|
||||
{
|
||||
enable_smi(EOS);
|
||||
pmc_enable_smi(EOS);
|
||||
}
|
||||
|
||||
static void busmaster_disable_on_bus(int bus)
|
||||
|
|
@ -136,7 +137,7 @@ static void southbridge_smi_sleep(void)
|
|||
outb(tmp72, 0x72);
|
||||
|
||||
/* First, disable further SMIs */
|
||||
disable_smi(SLP_SMI_EN);
|
||||
pmc_disable_smi(SLP_SMI_EN);
|
||||
|
||||
/* Figure out SLP_TYP */
|
||||
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
|
|
@ -152,7 +153,7 @@ static void southbridge_smi_sleep(void)
|
|||
elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
|
||||
|
||||
/* Clear pending GPE events */
|
||||
clear_gpe_status();
|
||||
pmc_clear_gpe_status();
|
||||
|
||||
/* Next, do the deed. */
|
||||
switch (slp_typ) {
|
||||
|
|
@ -175,7 +176,7 @@ static void southbridge_smi_sleep(void)
|
|||
/*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
|
||||
s5pwr = MAINBOARD_POWER_ON;
|
||||
/* Disable all GPE */
|
||||
disable_all_gpe();
|
||||
pmc_disable_all_gpe();
|
||||
|
||||
/*
|
||||
* Always set the flag in case CMOS was changed on runtime. For
|
||||
|
|
@ -201,7 +202,7 @@ static void southbridge_smi_sleep(void)
|
|||
* event again. We need to set BIT13 (SLP_EN) though to make the
|
||||
* sleep happen.
|
||||
*/
|
||||
enable_pm1_control(SLP_EN);
|
||||
pmc_enable_pm1_control(SLP_EN);
|
||||
|
||||
/* Make sure to stop executing code here for S3/S4/S5 */
|
||||
if (slp_typ >= ACPI_S3)
|
||||
|
|
@ -215,7 +216,7 @@ static void southbridge_smi_sleep(void)
|
|||
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
|
||||
if (reg32 & SCI_EN) {
|
||||
/* The OS is not an ACPI OS, so we set the state to S0 */
|
||||
disable_pm1_control(SLP_EN | SLP_TYP);
|
||||
pmc_disable_pm1_control(SLP_EN | SLP_TYP);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -306,11 +307,11 @@ static void southbridge_smi_apmc(void)
|
|||
printk(BIOS_DEBUG, "P-state control\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
disable_pm1_control(SCI_EN);
|
||||
pmc_disable_pm1_control(SCI_EN);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
|
||||
break;
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
enable_pm1_control(SCI_EN);
|
||||
pmc_enable_pm1_control(SCI_EN);
|
||||
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
|
||||
break;
|
||||
case APM_CNT_FINALIZE:
|
||||
|
|
@ -341,8 +342,8 @@ static void southbridge_smi_apmc(void)
|
|||
|
||||
static void southbridge_smi_pm1(void)
|
||||
{
|
||||
u16 pm1_sts = clear_pm1_status();
|
||||
u16 pm1_en = read_pm1_enable();
|
||||
u16 pm1_sts = pmc_clear_pm1_status();
|
||||
u16 pm1_en = pmc_read_pm1_enable();
|
||||
|
||||
/*
|
||||
* While OSPM is not active, poweroff immediately on a power button
|
||||
|
|
@ -352,14 +353,14 @@ static void southbridge_smi_pm1(void)
|
|||
/* power button pressed */
|
||||
if (IS_ENABLED(CONFIG_ELOG_GSMI))
|
||||
elog_add_event(ELOG_TYPE_POWER_BUTTON);
|
||||
disable_pm1_control(-1UL);
|
||||
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
|
||||
pmc_disable_pm1_control(-1UL);
|
||||
pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
|
||||
}
|
||||
}
|
||||
|
||||
static void southbridge_smi_gpe0(void)
|
||||
{
|
||||
clear_gpe_status();
|
||||
pmc_clear_gpe_status();
|
||||
}
|
||||
|
||||
void __attribute__((weak))
|
||||
|
|
@ -395,7 +396,7 @@ static void southbridge_smi_mc(void)
|
|||
|
||||
static void southbridge_smi_tco(void)
|
||||
{
|
||||
u32 tco_sts = clear_tco_status();
|
||||
u32 tco_sts = pmc_clear_tco_status();
|
||||
|
||||
/* Any TCO event? */
|
||||
if (!tco_sts)
|
||||
|
|
@ -522,7 +523,7 @@ void southbridge_smi_handler(void)
|
|||
* We need to clear the SMI status registers, or we won't see what's
|
||||
* happening in the following calls.
|
||||
*/
|
||||
smi_sts = clear_smi_status();
|
||||
smi_sts = pmc_clear_smi_status();
|
||||
|
||||
/* Call SMI sub handler for each of the status bits */
|
||||
for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue