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intel/fsp_model_406dx: Load APs microcode in model_406dx_init

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Load microcode to APs when performing model_406dx_init. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.

Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e
Signed-off-by: David Guckian <david.guckian@intel.com>
Reviewed-on: http://review.coreboot.org/12436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
David Guckian 2015-11-14 16:01:33 +00:00 committed by Martin Roth
parent 5f06d53bdb
commit d35c264b71
2 changed files with 5 additions and 1 deletions
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2
src/cpu/intel/fsp_model_406dx/Kconfig
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@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS
select SMP select SMP
select SSE2 select SSE2
select UDELAY_LAPIC select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER

4
src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View file

@ -22,6 +22,7 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/name.h> #include <cpu/x86/name.h>
#include "model_406dx.h" #include "model_406dx.h"
@ -168,6 +169,9 @@ static void model_406dx_init(struct device *cpu)
/* Turn on caching if we haven't already */ /* Turn on caching if we haven't already */
x86_enable_cache(); x86_enable_cache();
/* Load microcode */
intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */ /* Clear out pending MCEs */
configure_mca(); configure_mca();