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soc/intel/cannonlake: Disable USB2 PHY Power gating 

Workaround to disable USB2 PHY power gating to fix issue seen when
Apple 87W USB-C charger is connected in S0ix state on WHL platforms
(based on Intel's recommendation).  Issue is seen on CML platforms also.
So, disable power gating for Drallion too.

Add devicetree entry to set the flag to disable USB2 PHY power gating
for different CNL PCH based platforms

BUG=b:133775942
TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if
the system wakes up after that

Signed-off-by: Surendranath Gurivireddy <surendranath.r.gurivireddy@intel.com>
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Surendranath Gurivireddy 2019-10-31 15:45:39 -07:00 committed by Patrick Georgi
parent b0f15f0f86
commit d367503147
5 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -38,6 +38,8 @@ chip soc/intel/cannonlake
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
register "PchUnlockGpioPads" = "1"
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"

2
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View File

@ -27,6 +27,8 @@ chip soc/intel/cannonlake
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
register "PchUnlockGpioPads" = "1"
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "psys_pmax" = "140"

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View File

@ -30,6 +30,8 @@ chip soc/intel/cannonlake
register "PchPmSlpS4MinAssert" = "4" # 4s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
# USB2 PHY Power gating
register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1"
register "s0ix_enable" = "1"

2
src/soc/intel/cannonlake/chip.h
View File

@ -130,6 +130,8 @@ struct soc_intel_cannonlake_config {
uint16_t usb2_wake_enable_bitmap;
/* Wake Enable Bitmap for USB3 ports */
uint16_t usb3_wake_enable_bitmap;
/* USB2 PHY power gating */
uint8_t PchUsb2PhySusPgDisable;
/* SATA related */
enum {

3
src/soc/intel/cannonlake/fsp_params.c
View File

@ -273,6 +273,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
}
if (config->PchUsb2PhySusPgDisable)
params->PchUsb2PhySusPgEnable = 0;
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;