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soc/intel/apollolake: Implement SPI flash status register read 

This was a dummy implementation until now which returned -1 always. Add
support for reading SPI flash status register (srp0).

BUG=chrome-os-partner:59267
BRANCH=None
TEST=Verified by enabling and disabling write-protect on reef that the
value of SRP0 changes accordingly in status register read.

Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-11-01 21:33:12 -07:00 committed by Furquan Shaikh
parent 6372a0eef1
commit d36ed272b2
1 changed files with 10 additions and 2 deletions
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12
src/soc/intel/apollolake/spi.c
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@ -313,8 +313,16 @@ static int nuclear_spi_write(struct spi_flash *flash,
static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg)
{
printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__);
return E_NOT_IMPLEMENTED;
int ret;
BOILERPLATE_CREATE_CTX(ctx);
ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
sizeof(*reg));
if (ret != SUCCESS)
return ret;
drain_xfer_fifo(ctx, reg, sizeof(*reg));
return ret;
}
static struct spi_slave boot_spi CAR_GLOBAL;