superio/nuvoton/nct6687d: Add ramstage driver and ACPI
TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via devicetree. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
Felix Held
parent
6cf9b8f8ac
commit
d3b8321563
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# SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the NCT6687D SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x1 PP Implemented, untested
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* 0x2 SP1 Implemented, untested
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* 0x3 SP1 Implemented, untested
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* 0x5 KBC Implemented, untested
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* 0x8 GPIO Implemented, untested
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* 0xb EC Implemented, untested
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* NCT6687D_SHOW_PP If defined, the parallel port will be exposed.
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* NCT6687D_SHOW_SP1 If defined, Serial Port 1 will be exposed.
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* NCT6687D_SHOW_SP2 If defined, Serial Port 2 will be exposed.
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* NCT6687D_SHOW_KBC If defined, the Keyboard Controller will be exposed.
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* NCT6687D_SHOW_GPIO If defined, GPIO support will be exposed.
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* NCT6687D_SHOW_EC If defined, the Environment Controller will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME NCT6687D
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("Nuvoton NCT6687D Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8,
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}
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IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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ACT1, 1, /* Logical device activation */
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ACT2, 1, /* Logical device activation */
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ACT3, 1, /* Logical device activation */
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ACT4, 1, /* Logical device activation */
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ACT5, 1, /* Logical device activation */
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ACT6, 1, /* Logical device activation */
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ACT7, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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Offset (0x74),
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PNP_DMA0, 8, /* DRQ */
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x87
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef NCT6687D_SHOW_PP
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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/*
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* The extra code required to dynamically reflect ECP in the HID
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* isn't currently justified, so the HID is hardcoded as not
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* using ECP. "PNP0401" would indicate ECP.
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*/
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#define SUPERIO_PNP_HID "PNP0400"
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#define SUPERIO_PNP_LDN 1
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#define SUPERIO_PNP_DMA
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef NCT6687D_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef NCT6687D_SHOW_SP2
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 3
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef NCT6687D_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#define SUPERIO_KBC_PS2M
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef NCT6687D_SHOW_EC
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 11
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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@ -0,0 +1,92 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <option.h>
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#include <superio/conf_mode.h>
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#include "nct6687d.h"
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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/* 0xeb register definitions */
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#define NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK 0x60
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#define NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT 5
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#define NCT6687D_ACPI_POWER_ALWAYS_OFF (0 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT)
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#define NCT6687D_ACPI_POWER_ALWAYS_ON (1 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT)
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#define NCT6687D_ACPI_POWER_PREV_STATE (2 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT)
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#define NCT6687D_ACPI_POWER_USER_DEFINED (3 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT)
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static void nct6687d_init(struct device *dev)
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{
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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/* TODO: Might potentially need code for EC, GPIOs, etc. */
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case NCT6687D_KBC:
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pc_keyboard_init(PROBE_AUX_DEVICE);
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break;
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case NCT6687D_ACPI:
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uint8_t byte;
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uint8_t power_status;
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/* Set power state after power fail */
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power_status = get_uint_option("power_on_after_fail",
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CONFIG_MAINBOARD_POWER_FAILURE_STATE);
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pnp_enter_conf_mode(dev);
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pnp_set_logical_device(dev);
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byte = pnp_read_config(dev, 0xeb);
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byte &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK;
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if (power_status == MAINBOARD_POWER_ON)
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byte |= NCT6687D_ACPI_POWER_ALWAYS_ON;
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else if (power_status == MAINBOARD_POWER_KEEP)
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byte |= NCT6687D_ACPI_POWER_PREV_STATE;
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pnp_write_config(dev, 0xeb, byte);
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pnp_exit_conf_mode(dev);
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printk(BIOS_INFO, "set power %s after power fail\n",
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power_status ? "on" : "off");
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_alt_enable,
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.init = nct6687d_init,
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.ops_pnp_mode = &pnp_conf_mode_8787_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ NULL, NCT6687D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0, 0x0FF8,},
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{ NULL, NCT6687D_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0FF8, },
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{ NULL, NCT6687D_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, 0x0FF8, },
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{ NULL, NCT6687D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0,
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0x0FFF, 0x0FFF, },
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{ NULL, NCT6687D_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3,
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0x0FF8, },
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{ NULL, NCT6687D_GPIO_0_7, PNP_IO0 | PNP_IRQ0, 0x0FF0,},
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{ NULL, NCT6687D_P80_UART},
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{ NULL, NCT6687D_GPIO_8_9_AF},
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{ NULL, NCT6687D_ACPI, PNP_IO0 | PNP_IRQ0, 0x0FF8,},
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{ NULL, NCT6687D_EC, PNP_IO0 | PNP_IRQ0, 0x0FF8,},
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{ NULL, NCT6687D_RTC},
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{ NULL, NCT6687D_SLEEP_PWR},
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{ NULL, NCT6687D_TACH_PWM},
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{ NULL, NCT6687D_FREG},
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};
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static void enable_dev(struct device *dev)
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{
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pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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struct chip_operations superio_nuvoton_nct6687d_ops = {
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CHIP_NAME("NUVOTON NCT6687D Super I/O")
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.enable_dev = enable_dev,
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};
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