soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Skylake systems like Cave and Caroline. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update caroline coreboot and test i/o latency is under 100ms Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18532 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -20,6 +20,7 @@ Device (EMMC)
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{
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Name (_ADR, 0x001E0004)
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Name (_DDN, "eMMC Controller")
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Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
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OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
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Field (EMCR, DWordAcc, NoLock, Preserve)
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@ -31,6 +32,48 @@ Device (EMMC)
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PGEN, 1, /* PG_ENABLE */
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}
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (LEqual (Arg0, ^UUID)) {
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/*
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* Function 9: Device Readiness Durations
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* Returns a package of five integers covering
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* various device related delay in PCIe Base Spec.
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*/
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If (LEqual (Arg2, 9)) {
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/*
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* Function 9 support for revision 3.
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* ECN link for function definitions
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* [https://pcisig.com/sites/default/files/
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* specification_documents/
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* ECN_fw_latency_optimization_final.pdf]
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*/
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If (LEqual (Arg1, 3)) {
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/*
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* Integer 0: FW reset time.
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* Integer 1: FW data link up time.
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* Integer 2: FW functional level reset
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* time.
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* Integer 3: FW D3 hot to D0 time.
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* Integer 4: FW VF enable time.
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* set ACPI constant Ones for elements
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* where overriding the default value
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* is not desired.
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*/
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Return (Package (5) {0, Ones, Ones,
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Ones, Ones})
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}
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}
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}
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Return (Buffer() { 0x00 })
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}
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Method (_PS0, 0, Serialized)
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{
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/* Disable Power Gate */
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