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mb/google/brya/var/omnigul: Add SOC I2C config 

Add SoC config and .early_init = 1 in I2C1

BUG=b:263060849
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
This commit is contained in:
Jamie Chen 2023-02-07 18:02:41 +08:00 committed by Eric Lai
parent 26d7303f01
commit d4658ebcdf
1 changed files with 27 additions and 0 deletions
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27
src/mainboard/google/brya/variants/omnigul/overridetree.cb
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@ -10,6 +10,33 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C3 | TouchScreen |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,