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mb/google/poppy/variants/soraka: Tune I2C5 params 

This change updates scl_lcnt value for I2C5 to bring the bus frequency
closer to 400kHz.

BUG=b:65062416
TEST=Verified that I2C5 frequency is between 389-396kHz.

Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-12-08 11:58:37 -08:00 committed by Furquan Shaikh
parent 2bbc3dc28d
commit d46e216d00
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/poppy/variants/soraka/devicetree.cb
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@ -226,7 +226,7 @@ chip soc/intel/skylake
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.speed_config[0] = { .speed_config[0] = {
.speed = I2C_SPEED_FAST, .speed = I2C_SPEED_FAST,
.scl_lcnt = 195, .scl_lcnt = 190,
.scl_hcnt = 90, .scl_hcnt = 90,
.sda_hold = 36, .sda_hold = 36,
}, },