soc/intel/meteorlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Rex successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -119,23 +119,23 @@ static void save_dimm_info(void)
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void mainboard_romstage_entry(void)
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void mainboard_romstage_entry(void)
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{
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{
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bool s3wake;
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struct chipset_power_state *ps = pmc_get_power_state();
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struct chipset_power_state *ps = pmc_get_power_state();
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bool s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program SMBus base address and enable it */
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smbus_common_init();
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/* Initialize HECI interface */
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/* Initialize HECI interface */
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cse_init(HECI1_BASE_ADDRESS);
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cse_init(HECI1_BASE_ADDRESS);
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s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
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if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
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timestamp_add_now(TS_CSE_FW_SYNC_START);
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timestamp_add_now(TS_CSE_FW_SYNC_START);
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cse_fw_sync();
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cse_fw_sync();
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timestamp_add_now(TS_CSE_FW_SYNC_END);
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timestamp_add_now(TS_CSE_FW_SYNC_END);
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}
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}
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program SMBus base address and enable it */
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smbus_common_init();
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/*
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/*
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* Set low maximum temp threshold value used for dynamic thermal sensor
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* Set low maximum temp threshold value used for dynamic thermal sensor
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* shutdown consideration.
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* shutdown consideration.
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