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mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree 

BUG=b:149970243
BRANCH=zork

Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-08-28 02:12:52 +02:00 committed by Patrick Georgi
parent 764b987a6f
commit d555d6a88c
1 changed files with 9 additions and 0 deletions
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9
src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
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@ -180,6 +180,15 @@ chip soc/amd/picasso
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
# genral purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD
register "gpp_clk_config[3]" = "GPP_CLK_OFF"
register "gpp_clk_config[4]" = "GPP_CLK_OFF"
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end