rush: Convert rush initialization to use funitcfg api
Use funitcfg api for bootblock, romstage as well as ramstage initialization in rush. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully and boots till last known good point. Change-Id: I243597de9ec13904a2bb58a04b402f9545424760 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211766 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8922 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -24,6 +24,7 @@
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#include <soc/bootblock.h>
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#include <soc/clock.h>
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#include <soc/padconfig.h>
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#include <soc/funitcfg.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra132/clk_rst.h>
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#include <soc/nvidia/tegra132/spi.h> /* FIXME: move back to soc code? */
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@ -51,9 +52,15 @@ static const struct pad_config padcfgs[] = {
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PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
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PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
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PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
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};
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static const struct pad_config i2cpad[] = {
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/* PMIC i2C bus */
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PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
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PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
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};
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static const struct pad_config spipad[] = {
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/* SPI fLash: mosi, miso, clk, cs0 */
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PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
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PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
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@ -61,6 +68,11 @@ static const struct pad_config padcfgs[] = {
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PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
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};
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static const struct funit_cfg funitcfgs[] = {
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FUNIT_CFG(I2C5, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
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FUNIT_CFG(SBC4, PLLP, 33333, spipad, ARRAY_SIZE(spipad)),
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};
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void bootblock_mainboard_early_init(void)
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{
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soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
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@ -70,24 +82,15 @@ static void set_clock_sources(void)
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{
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/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
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writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
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/* The PMIC is on I2C5 and can run at 400 KHz. */
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clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
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/* TODO: We should be able to set this to 50MHz, but that did not seem
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* reliable. */
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clock_configure_source(sbc4, PLLP, 33333);
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}
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void bootblock_mainboard_init(void)
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{
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set_clock_sources();
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/* Enable PMIC I2C controller. */
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clock_enable_clear_reset(0, CLK_H_I2C5, 0, 0, 0, 0);
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/* Set up the pads required to load romstage. */
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soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
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soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
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i2c_init(4);
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pmic_init(4);
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@ -25,10 +25,9 @@
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#include <soc/nvidia/tegra132/spi.h>
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#include <soc/addressmap.h>
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#include <soc/padconfig.h>
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#include <soc/funitcfg.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static const struct pad_config padcfgs[] = {
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static const struct pad_config sdmmc3_pad[] = {
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/* MMC3(SDCARD) */
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PAD_CFG_SFIO(SDMMC3_CLK, PINMUX_INPUT_ENABLE, SDMMC3),
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PAD_CFG_SFIO(SDMMC3_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC3),
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@ -43,6 +42,9 @@ static const struct pad_config padcfgs[] = {
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/* Disable SD card reader power so it can be reset even on warm boot.
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Payloads must enable power before accessing SD card slots. */
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PAD_CFG_GPIO_OUT0(KB_ROW0, PINMUX_PULL_NONE),
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};
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static const struct pad_config sdmmc4_pad[] = {
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/* MMC4 (eMMC) */
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PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE, SDMMC4),
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PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
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@ -56,13 +58,10 @@ static const struct pad_config padcfgs[] = {
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PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SDMMC4),
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};
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static void configure_clocks(void)
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{
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/* MMC */
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clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
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clock_configure_source(sdmmc3, PLLP, 48000);
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clock_configure_source(sdmmc4, PLLP, 48000);
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}
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static const struct funit_cfg funitcfgs[] = {
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FUNIT_CFG(SDMMC3, PLLP, 48000, sdmmc3_pad, ARRAY_SIZE(sdmmc3_pad)),
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FUNIT_CFG(SDMMC4, PLLP, 48000, sdmmc4_pad, ARRAY_SIZE(sdmmc4_pad)),
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};
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static void setup_ec_spi(void)
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{
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@ -73,9 +72,7 @@ static void setup_ec_spi(void)
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static void mainboard_init(device_t dev)
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{
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configure_clocks();
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soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
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soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
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setup_ec_spi();
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}
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@ -23,15 +23,20 @@
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#include <soc/clock.h>
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#include <soc/padconfig.h>
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#include <soc/nvidia/tegra/i2c.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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#include <soc/funitcfg.h>
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static const struct pad_config padcfgs[] = {
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/* SOC_WARM_RESET_L */
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PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
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};
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static const struct pad_config i2cpad[] = {
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/* TPM I2C */
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PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
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PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
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};
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static const struct pad_config spipad[] = {
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/* EC on SPI1: mosi, miso, clk, cs */
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PAD_CFG_SFIO(ULPI_CLK, PINMUX_INPUT_ENABLE, SPI1),
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PAD_CFG_SFIO(ULPI_DIR, PINMUX_INPUT_ENABLE, SPI1),
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@ -39,23 +44,16 @@ static const struct pad_config padcfgs[] = {
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PAD_CFG_SFIO(ULPI_STP, PINMUX_INPUT_ENABLE, SPI1),
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};
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static void configure_clocks(void)
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{
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/* EC on SPI1 controller. */
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clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
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clock_configure_source(sbc1, CLK_M, 3000);
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/* TPM on I2C3 controller */
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clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
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clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
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}
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static const struct funit_cfg funitcfgs[] = {
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FUNIT_CFG(SBC1, CLK_M, 3000, spipad, ARRAY_SIZE(spipad)),
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FUNIT_CFG(I2C3, PLLP, 400, i2cpad, ARRAY_SIZE(i2cpad)),
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};
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void romstage_mainboard_init(void)
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{
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configure_clocks();
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/* Bring up controller interfaces for ramstage loading. */
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soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
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soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
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/* TPM I2C bus */
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i2c_init(2);
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