sync the northbridge.c with other family.
Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -25,7 +25,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
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device pci_domain 0 on
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device pci_domain 0 on
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subsystemid 0x1022 0x1410 inherit
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subsystemid 0x1022 0x1410 inherit
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chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
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chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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device pci 18.0 on # northbridge
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chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
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chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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@ -37,6 +37,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
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device pci 6.0 on end # PCIE Slot1 x1
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device pci 6.0 on end # PCIE Slot1 x1
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device pci 7.0 on end # LAN
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device pci 7.0 on end # LAN
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device pci 8.0 off end # NB/SB Link P2P bridge
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device pci 8.0 off end # NB/SB Link P2P bridge
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end
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end
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end
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chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
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chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
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device pci 10.0 on end # XHCI HC0
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device pci 10.0 on end # XHCI HC0
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@ -74,7 +75,7 @@ chip northbridge/amd/agesa/family15tn/root_complex
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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register "gpp_configuration" = "4"
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register "gpp_configuration" = "4"
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end #southbridge/amd/hudson
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end #southbridge/amd/hudson
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device pci 18.0 on end
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# device pci 18.0 on end
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#device pci 18.0 on end
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#device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.2 on end
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@ -55,8 +55,8 @@ int add_mainboard_resources(struct lb_memory *mem)
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/* UMA is removed from system memory in the northbridge code, but
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/* UMA is removed from system memory in the northbridge code, but
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* in some circumstances we want the memory mentioned as reserved.
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* in some circumstances we want the memory mentioned as reserved.
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*/
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*/
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/* TODO: Check out why it is commented. */
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/* TODO: Check out why it was commented. */
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#if 0 /* (CONFIG_GFXUMA == 1) */
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#if CONFIG_GFXUMA
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printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
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printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
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uma_memory_base, uma_memory_size);
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uma_memory_base, uma_memory_size);
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lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
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lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
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@ -399,7 +399,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
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* we only deal with the 'first' vga card */
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* we only deal with the 'first' vga card */
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for (link = dev->link_list; link; link = link->next) {
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for (link = dev->link_list; link; link = link->next) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
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#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
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#if CONFIG_MULTIPLE_VGA_ADAPTERS
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extern device_t vga_pri; // the primary vga device, defined in device.c
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extern device_t vga_pri; // the primary vga device, defined in device.c
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
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link->secondary,link->subordinate);
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link->secondary,link->subordinate);
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@ -447,12 +447,35 @@ static void northbridge_init(struct device *dev)
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{
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{
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}
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}
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static unsigned scan_chains(device_t dev, unsigned max)
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{
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unsigned nodeid;
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struct bus *link;
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device_t io_hub = NULL;
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u32 next_unitid = 0x18;
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nodeid = amdfam15_nodeid(dev);
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if (nodeid == 0) {
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for (link = dev->link_list; link; link = link->next) {
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//if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */
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if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
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io_hub = link->children;
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if (!io_hub || !io_hub->enabled) {
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die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
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}
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/* Now that nothing is overlapping it is safe to scan the children. */
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max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0);
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}
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}
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}
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return max;
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}
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static struct device_operations northbridge_operations = {
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static struct device_operations northbridge_operations = {
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.read_resources = read_resources,
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.read_resources = read_resources,
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.set_resources = set_resources,
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.set_resources = set_resources,
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.enable_resources = pci_dev_enable_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.init = northbridge_init,
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.scan_bus = 0, /*scan_chains, */
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.scan_bus = scan_chains,
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.enable = 0,
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.enable = 0,
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.ops_pci = 0,
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.ops_pci = 0,
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};
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};
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@ -508,7 +531,7 @@ static void domain_read_resources(device_t dev)
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/* FIXME: do we need to check extend conf space?
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/* FIXME: do we need to check extend conf space?
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I don't believe that much preset value */
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I don't believe that much preset value */
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#if CONFIG_PCI_64BIT_PREF_MEM == 0
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#if !CONFIG_PCI_64BIT_PREF_MEM
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pci_domain_read_resources(dev);
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pci_domain_read_resources(dev);
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#else
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#else
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@ -663,7 +686,7 @@ void setup_uma_memory(void)
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static void domain_set_resources(device_t dev)
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static void domain_set_resources(device_t dev)
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{
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{
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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#if CONFIG_PCI_64BIT_PREF_MEM
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struct resource *io, *mem1, *mem2;
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struct resource *io, *mem1, *mem2;
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struct resource *res;
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struct resource *res;
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#endif
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#endif
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@ -676,7 +699,7 @@ static void domain_set_resources(device_t dev)
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u32 reset_memhole = 1;
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u32 reset_memhole = 1;
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#endif
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#endif
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#if CONFIG_PCI_64BIT_PREF_MEM == 1
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#if CONFIG_PCI_64BIT_PREF_MEM
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for (link = dev->link_list; link; link = link->next) {
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for (link = dev->link_list; link; link = link->next) {
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/* Now reallocate the pci resources memory with the
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/* Now reallocate the pci resources memory with the
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@ -791,10 +814,10 @@ static void domain_set_resources(device_t dev)
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ram_resource(dev, (idx | i), basek, pre_sizek);
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ram_resource(dev, (idx | i), basek, pre_sizek);
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idx += 0x10;
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idx += 0x10;
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sizek -= pre_sizek;
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sizek -= pre_sizek;
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#if CONFIG_WRITE_HIGH_TABLES==1
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#if CONFIG_WRITE_HIGH_TABLES
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if (high_tables_base==0) {
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if (high_tables_base==0) {
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/* Leave some space for ACPI, PIRQ and MP tables */
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA
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high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
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high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
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#else
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#else
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high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
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high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
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@ -818,12 +841,12 @@ static void domain_set_resources(device_t dev)
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ram_resource(dev, (idx | i), basek, sizek);
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ram_resource(dev, (idx | i), basek, sizek);
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idx += 0x10;
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idx += 0x10;
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#if CONFIG_WRITE_HIGH_TABLES==1
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#if CONFIG_WRITE_HIGH_TABLES
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printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
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printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
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i, mmio_basek, basek, limitk);
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i, mmio_basek, basek, limitk);
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if (high_tables_base==0) {
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if (high_tables_base==0) {
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/* Leave some space for ACPI, PIRQ and MP tables */
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/* Leave some space for ACPI, PIRQ and MP tables */
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#if CONFIG_GFXUMA == 1
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#if CONFIG_GFXUMA
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high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
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high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
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#else
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#else
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high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
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high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
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@ -1018,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
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* otherwise the device under it will not be scanned
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* otherwise the device under it will not be scanned
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*/
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*/
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int linknum;
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int linknum;
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#if CONFIG_HT3_SUPPORT==1
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#if CONFIG_HT3_SUPPORT
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linknum = 8;
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linknum = 8;
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#else
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#else
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linknum = 4;
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linknum = 4;
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