soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

This patch creates a helper function to clear HSFSTS_CTL (offset 0x04)
register Bits 0 to 4.

As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation,
it's important to clear all SPI outstanding status before setting SPI
lock bits.

BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -428,3 +428,11 @@ void fast_spi_disable_wp(void)
 	bios_cntl |= SPI_BIOS_CONTROL_WPD;
 	pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
 }
+
+void fast_spi_clear_outstanding_status(void)
+{
+	void *spibar = fast_spi_get_bar();
+
+	/* Make sure all W1C status bits get cleared. */
+	write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS);
+}

src/soc/intel/common/block/include/intelblocks/fast_spi.h

@@ -5,6 +5,8 @@
 
 #include <types.h>
 
+/* Clear any SPI outstanding status bits, i.e., FCERR, FDONE etc. */
+void fast_spi_clear_outstanding_status(void);
 /* Check if SPI transaction is pending */
 int fast_spi_cycle_in_progress(void);
 /*