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soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run 

This change reconfigures SPI speeds after FSP-S has run since
FSP-S is currently configuring the SPI frequency when it should
not. Until FSP-S behavior is fixed, this workaround needs to be
applied.

BUG=b:153506142
TEST=Verified that em100 works fine.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-06-10 15:35:44 -07:00
parent 6740647cfd
commit d5f1e0f973
1 changed files with 8 additions and 0 deletions
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8
src/soc/amd/picasso/chip.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/spi.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@ -164,6 +165,13 @@ static void soc_init(void *chip_info)
fsp_silicon_init(acpi_is_wakeup_s3());
/*
* TODO(furquan): Get rid of this once FSP is fixed to not touch SPI
* registers(b/153506142). Currently, FSP-S reconfigures SPI frequency causing em100 to
* stop working. Thus, reconfigure SPI speeds here.
*/
fch_spi_config_modes();
data_fabric_set_mmio_np();
southbridge_init(chip_info);
}