GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/stoneyridge: Add USB settings to gnvs 

A later patch will rely on two USB settings from the BIOS.  Add these
to the global_gnvs_t structure.

The first is a data that will be used to locate the xHCI firmware for
reloading after a resume.  Although the existing calculations will be
somewhat simple, keeping this on the coreboot side will help in the
event multiple FWs are eventually in the build.

The second item is a usable EHCI base address that may be programmed
during S3 suspend and resume.  At the time the PTS and WAK code runs,
the BAR will be clear.

BUG=b:77602074

Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2018-09-27 08:31:02 -06:00 committed by Martin Roth
parent fc458cdc53
commit d61e347bff
2 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/amd/stoneyridge/acpi/globalnvs.asl
View File

@ -66,6 +66,11 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
, 2,
ESPI, 1, // ESPI, 27
, 4,
FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM
FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM
FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM
FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM
EH10, 32, // 0x44 - EHCI BAR
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>

7
src/soc/amd/stoneyridge/include/soc/nvs.h
View File

@ -53,7 +53,12 @@ typedef struct global_nvs_t {
uint8_t tmax; /* 0x30 - CPU Tj_max */
uint8_t pad1[3];
aoac_devs_t aoac; /* 0x34 - AOAC device enables */
uint8_t unused[200];
uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */
uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */
uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */
uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */
uint32_t eh10; /* 0x40 - EHCI BAR */
uint8_t unused[184];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;