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Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb. 

Since we have CBFS setting rom_address in board files is no longer 
necessary.

Also, drop vga_rom_address from RS690 completely, it was never used 
in the code.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2009-11-06 17:11:05 +00:00 committed by Myles Watson
parent eeec0ef00a
commit d63085b20e
73 changed files with 0 additions and 125 deletions
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1
src/mainboard/amd/dbm690t/Config.lb
View File

@ -157,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

1
src/mainboard/amd/dbm690t/devicetree.cb
View File

@ -22,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

1
src/mainboard/amd/pistachio/Config.lb
View File

@ -158,7 +158,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

1
src/mainboard/amd/pistachio/devicetree.cb
View File

@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913

1
src/mainboard/arima/hdama/Config.lb
View File

@ -179,7 +179,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end # LAN
chip drivers/pci/onboard
device pci 6.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
## PCI Slot 5 (correct?)
#chip drivers/generic/generic

1
src/mainboard/arima/hdama/devicetree.cb
View File

@ -75,7 +75,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end # LAN
chip drivers/pci/onboard
device pci 6.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
## PCI Slot 5 (correct?)
#chip drivers/generic/generic

3
src/mainboard/asi/mb_5blmp/Config.lb
View File

@ -138,9 +138,6 @@ chip northbridge/amd/gx1 # Northbridge
# device pci 12.4 on # VGA (onboard)
# chip drivers/pci/onboard
# device pci 12.4 on end
# register "rom_address" = "0xfffc0000" # 256 KB image
# # register "rom_address" = "0xfff80000" # 512 KB image
# # register "rom_address" = "0xfff00000" # 1 MB image
# end
# end
device pci 13.0 on end # USB

3
src/mainboard/asi/mb_5blmp/devicetree.cb
View File

@ -40,9 +40,6 @@ chip northbridge/amd/gx1 # Northbridge
# device pci 12.4 on # VGA (onboard)
# chip drivers/pci/onboard
# device pci 12.4 on end
# register "rom_address" = "0xfffc0000" # 256 KB image
# # register "rom_address" = "0xfff80000" # 512 KB image
# # register "rom_address" = "0xfff00000" # 1 MB image
# end
# end
device pci 13.0 on end # USB

2
src/mainboard/asus/mew-vm/Config.lb
View File

@ -99,7 +99,6 @@ chip northbridge/intel/i82810
device pci 1.0 on # Onboard Video
#chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
#end
end
chip southbridge/intel/i82801xx # Southbridge
@ -109,7 +108,6 @@ chip northbridge/intel/i82810
device pci 1e.0 on # PCI Bridge
#chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
#end
end
device pci 1f.0 on # ISA/LPC? Bridge

2
src/mainboard/asus/mew-vm/devicetree.cb
View File

@ -4,7 +4,6 @@ chip northbridge/intel/i82810
device pci 1.0 on # Onboard Video
#chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
#end
end
chip southbridge/intel/i82801xx # Southbridge
@ -14,7 +13,6 @@ chip northbridge/intel/i82810
device pci 1e.0 on # PCI Bridge
#chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
#end
end
device pci 1f.0 on # ISA/LPC? Bridge

2
src/mainboard/broadcom/blast/Config.lb
View File

@ -211,7 +211,6 @@ chip northbridge/amd/amdk8/root_complex
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
register "rom_address" = "0xfff80000"
end
end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
@ -220,7 +219,6 @@ chip northbridge/amd/amdk8/root_complex
# end
# chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# register "rom_address" = "0xfff80000"
# end

2
src/mainboard/broadcom/blast/devicetree.cb
View File

@ -109,7 +109,6 @@ chip northbridge/amd/amdk8/root_complex
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
register "rom_address" = "0xfff80000"
end
end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
@ -118,7 +117,6 @@ chip northbridge/amd/amdk8/root_complex
# end
# chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# register "rom_address" = "0xfff80000"
# end

1
src/mainboard/digitallogic/msm586seg/Config.lb
View File

@ -108,7 +108,6 @@ chip cpu/amd/sc520
end
chip drivers/pci/onboard
device pci 14.0 on end # 69000
register "rom_address" = "0x2000000"
end
# register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"

1
src/mainboard/digitallogic/msm586seg/devicetree.cb
View File

@ -7,7 +7,6 @@ chip cpu/amd/sc520
end
chip drivers/pci/onboard
device pci 14.0 on end # 69000
register "rom_address" = "0x2000000"
end
# register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"

1
src/mainboard/gigabyte/ga_2761gxdk/Config.lb
View File

@ -180,7 +180,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # AGP bridge
chip drivers/pci/onboard # Integrated VGA
device pci 0.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 2.0 on # LPC

1
src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
View File

@ -13,7 +13,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # AGP bridge
chip drivers/pci/onboard # Integrated VGA
device pci 0.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 2.0 on # LPC

1
src/mainboard/hp/e_vectra_p2706t/Config.lb
View File

@ -78,7 +78,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"

1
src/mainboard/hp/e_vectra_p2706t/devicetree.cb
View File

@ -9,7 +9,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"

1
src/mainboard/ibm/e326/Config.lb
View File

@ -127,7 +127,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 5.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/ibm/e326/devicetree.cb
View File

@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 5.0 on end # ATI Rage XL
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

3
src/mainboard/intel/d945gclf/Config.lb
View File

@ -152,9 +152,6 @@ chip northbridge/intel/i945
device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard
device pci 02.0 on end # vga controller
# register "rom_address" = "0xfffc0000" # 256 KB image
# register "rom_address" = "0xfff80000" # 512 KB image
# register "rom_address" = "0xfff00000" # 1 MB image
end
device pci 02.1 on end # display controller

3
src/mainboard/intel/d945gclf/devicetree.cb
View File

@ -30,9 +30,6 @@ chip northbridge/intel/i945
device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard
device pci 02.0 on end # vga controller
# register "rom_address" = "0xfffc0000" # 256 KB image
# register "rom_address" = "0xfff80000" # 512 KB image
# register "rom_address" = "0xfff00000" # 1 MB image
end
device pci 02.1 on end # display controller

1
src/mainboard/iwill/dk8_htx/Config.lb
View File

@ -234,7 +234,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
#chip drivers/pci/onboard
# device pci 6.0 on end
# register "rom_address" = "0xfff80000"
#end
end
device pci 1.0 on

1
src/mainboard/iwill/dk8_htx/devicetree.cb
View File

@ -26,7 +26,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
#chip drivers/pci/onboard
# device pci 6.0 on end
# register "rom_address" = "0xfff80000"
#end
end
device pci 1.0 on

3
src/mainboard/kontron/986lcd-m/Config.lb
View File

@ -155,9 +155,6 @@ chip northbridge/intel/i945
# device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard
device pci 02.0 on end # vga controller
# register "rom_address" = "0xfffc0000" # 256 KB image
# register "rom_address" = "0xfff80000" # 512 KB image
register "rom_address" = "0xfff00000" # 1 MB image
end
device pci 02.1 on end # display controller

3
src/mainboard/kontron/986lcd-m/devicetree.cb
View File

@ -11,9 +11,6 @@ chip northbridge/intel/i945
device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard
device pci 02.0 on end # vga controller
# register "rom_address" = "0xfffc0000" # 256 KB image
# register "rom_address" = "0xfff80000" # 512 KB image
register "rom_address" = "0xfff00000" # 1 MB image
end
device pci 02.1 on end # display controller

3
src/mainboard/kontron/kt690/Config.lb
View File

@ -134,7 +134,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -158,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -168,7 +166,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

3
src/mainboard/kontron/kt690/devicetree.cb
View File

@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff00000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

1
src/mainboard/mitac/6513wu/Config.lb
View File

@ -82,7 +82,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03"

1
src/mainboard/mitac/6513wu/devicetree.cb
View File

@ -28,7 +28,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03"

1
src/mainboard/msi/ms6178/Config.lb
View File

@ -77,7 +77,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"

1
src/mainboard/msi/ms6178/devicetree.cb
View File

@ -28,7 +28,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 1.0 on end
register "rom_address" = "0xfff80000" # 512 KB image
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"

2
src/mainboard/msi/ms9185/Config.lb
View File

@ -211,7 +211,6 @@ chip northbridge/amd/amdk8/root_complex
chip drivers/pci/onboard
device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
register "rom_address" = "0xfff80000"
end
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
@ -229,7 +228,6 @@ chip northbridge/amd/amdk8/root_complex
# end
# chip drivers/pci/onboard
# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# register "rom_address" = "0xfff80000"
# end
end # device pci 18.0

2
src/mainboard/msi/ms9185/devicetree.cb
View File

@ -77,7 +77,6 @@ chip northbridge/amd/amdk8/root_complex
chip drivers/pci/onboard
device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
register "rom_address" = "0xfff80000"
end
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
@ -95,7 +94,6 @@ chip northbridge/amd/amdk8/root_complex
# end
# chip drivers/pci/onboard
# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# register "rom_address" = "0xfff80000"
# end
end # device pci 18.0

1
src/mainboard/msi/ms9282/Config.lb
View File

@ -280,7 +280,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on #P2P
chip drivers/pci/onboard
device pci 4.0 on end
register "rom_address" = "0xfff80000"
end
end # P2P
device pci 7.0 on end # reserve

1
src/mainboard/msi/ms9282/devicetree.cb
View File

@ -139,7 +139,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on #P2P
chip drivers/pci/onboard
device pci 4.0 on end
register "rom_address" = "0xfff80000"
end
end # P2P
device pci 7.0 on end # reserve

1
src/mainboard/nec/powermate2000/Config.lb
View File

@ -78,7 +78,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1.0 off # Onboard video
# chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
# end
end
chip southbridge/intel/i82801xx # Southbridge

1
src/mainboard/nec/powermate2000/devicetree.cb
View File

@ -9,7 +9,6 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1.0 off # Onboard video
# chip drivers/pci/onboard
# device pci 1.0 on end
# register "rom_address" = "0xfff80000"
# end
end
chip southbridge/intel/i82801xx # Southbridge

1
src/mainboard/rca/rm4100/Config.lb
View File

@ -77,7 +77,6 @@ chip northbridge/intel/i82830 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 2.0 on end # VGA (Intel 82830 CGC)
register "rom_address" = "0xfff00000"
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05"

1
src/mainboard/rca/rm4100/devicetree.cb
View File

@ -3,7 +3,6 @@ chip northbridge/intel/i82830 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 2.0 on end # VGA (Intel 82830 CGC)
register "rom_address" = "0xfff00000"
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05"

2
src/mainboard/supermicro/h8dme/Config.lb
View File

@ -256,8 +256,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

2
src/mainboard/supermicro/h8dme/devicetree.cb
View File

@ -94,8 +94,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

2
src/mainboard/supermicro/h8dmr/Config.lb
View File

@ -278,8 +278,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

2
src/mainboard/supermicro/h8dmr/devicetree.cb
View File

@ -114,8 +114,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

2
src/mainboard/supermicro/h8dmr_fam10/Config.lb
View File

@ -282,8 +282,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

2
src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
View File

@ -116,8 +116,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 6.0 on # PCI
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000" #for 1M
# register "rom_address" = "0xfff80000" #for 512K
end
end
device pci 6.1 on end # AZA

9
src/mainboard/technexion/tim5690/Config.lb
View File

@ -134,7 +134,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff80000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -158,10 +157,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff80000" #512KB
#register "rom_address" = "0xfff00000" #1024KB
#register "rom_address" = "0xffe00000" #2048KB
#register "rom_address" = "0xffc00000" #4096KB
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -171,10 +166,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff80000"
#register "vga_rom_address" = "0xfff00000"
#register "vga_rom_address" = "0xffe00000"
#register "vga_rom_address" = "0xffc00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

9
src/mainboard/technexion/tim5690/devicetree.cb
View File

@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff80000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -23,10 +22,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff80000" #512KB
#register "rom_address" = "0xfff00000" #1024KB
#register "rom_address" = "0xffe00000" #2048KB
#register "rom_address" = "0xffc00000" #4096KB
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -36,10 +31,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff80000"
#register "vga_rom_address" = "0xfff00000"
#register "vga_rom_address" = "0xffe00000"
#register "vga_rom_address" = "0xffc00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

3
src/mainboard/technexion/tim8690/Config.lb
View File

@ -134,7 +134,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff80000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -158,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff80000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -168,7 +166,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff80000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

3
src/mainboard/technexion/tim8690/devicetree.cb
View File

@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff80000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x791F
register "rom_address" = "0xfff80000"
end
end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff80000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

1
src/mainboard/technologic/ts5300/Config.lb
View File

@ -109,7 +109,6 @@ chip cpu/amd/sc520
# end
# chip drivers/pci/onboard
# device pci 14.0 on end # 69000
# register "rom_address" = "0x2000000"
# end
# register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"

1
src/mainboard/technologic/ts5300/devicetree.cb
View File

@ -7,7 +7,6 @@ chip cpu/amd/sc520
# end
# chip drivers/pci/onboard
# device pci 14.0 on end # 69000
# register "rom_address" = "0x2000000"
# end
# register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}"

1
src/mainboard/thomson/ip1000/Config.lb
View File

@ -77,7 +77,6 @@ chip northbridge/intel/i82830 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 2.0 on end # VGA (Intel 82830 CGC)
register "rom_address" = "0xfff00000"
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05"

1
src/mainboard/thomson/ip1000/devicetree.cb
View File

@ -3,7 +3,6 @@ chip northbridge/intel/i82830 # Northbridge
device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA
device pci 2.0 on end # VGA (Intel 82830 CGC)
register "rom_address" = "0xfff00000"
end
chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05"

1
src/mainboard/tyan/s2850/Config.lb
View File

@ -121,7 +121,6 @@ chip northbridge/amd/amdk8/root_complex
#chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci b.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2850/devicetree.cb
View File

@ -19,7 +19,6 @@ chip northbridge/amd/amdk8/root_complex
#chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci b.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2875/Config.lb
View File

@ -125,7 +125,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 5.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2875/devicetree.cb
View File

@ -23,7 +23,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 5.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2880/Config.lb
View File

@ -140,7 +140,6 @@ chip northbridge/amd/amdk8/root_complex
end
chip drivers/pci/onboard
device pci 6.0 on end #adti
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2880/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/amd/amdk8/root_complex
end
chip drivers/pci/onboard
device pci 6.0 on end #adti
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2881/Config.lb
View File

@ -141,7 +141,6 @@ chip northbridge/amd/amdk8/root_complex
end
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2881/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/amd/amdk8/root_complex
end
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s2882/Config.lb
View File

@ -141,7 +141,6 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000"
end
chip drivers/pci/onboard
device pci 8.0 on end #intel 10/100

1
src/mainboard/tyan/s2882/devicetree.cb
View File

@ -39,7 +39,6 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff00000"
end
chip drivers/pci/onboard
device pci 8.0 on end #intel 10/100

1
src/mainboard/tyan/s2912_fam10/Config.lb
View File

@ -281,7 +281,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 6.0 on
chip drivers/pci/onboard
device pci 4.0 on end
register "rom_address" = "0xfff00000"
end
end # PCI
device pci 6.1 off end # AZA

1
src/mainboard/tyan/s2912_fam10/devicetree.cb
View File

@ -114,7 +114,6 @@ chip northbridge/amd/amdfam10/root_complex
device pci 6.0 on
chip drivers/pci/onboard
device pci 4.0 on end
register "rom_address" = "0xfff00000"
end
end # PCI
device pci 6.1 off end # AZA

1
src/mainboard/tyan/s4880/Config.lb
View File

@ -135,7 +135,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s4880/devicetree.cb
View File

@ -38,7 +38,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.0 off end
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
end
device pci 1.0 on

1
src/mainboard/tyan/s4882/Config.lb
View File

@ -134,7 +134,6 @@ chip northbridge/amd/amdk8/root_complex
#chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
chip drivers/pci/onboard
device pci 5.0 on end #SiI

1
src/mainboard/tyan/s4882/devicetree.cb
View File

@ -37,7 +37,6 @@ chip northbridge/amd/amdk8/root_complex
#chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
chip drivers/pci/onboard
device pci 5.0 on end #SiI

3
src/mainboard/via/vt8454c/Config.lb
View File

@ -123,9 +123,6 @@ chip northbridge/via/cx700
device pci 1.0 on # PCI Bridge
chip drivers/pci/onboard
device pci 0.0 on end
#register "rom_address" = "0xfffc0000" #256k image
register "rom_address" = "0xfff80000" #512k image
#register "rom_address" = "0xfff00000" #1024k image
end # Onboard Video
end # PCI Bridge
device pci f.0 on end # IDE/SATA

3
src/mainboard/via/vt8454c/devicetree.cb
View File

@ -14,9 +14,6 @@ chip northbridge/via/cx700
device pci 1.0 on # PCI Bridge
chip drivers/pci/onboard
device pci 0.0 on end
#register "rom_address" = "0xfffc0000" #256k image
register "rom_address" = "0xfff80000" #512k image
#register "rom_address" = "0xfff00000" #1024k image
end # Onboard Video
end # PCI Bridge
device pci f.0 on end # IDE/SATA

1
src/southbridge/amd/rs690/chip.h
View File

@ -23,7 +23,6 @@
/* Member variables are defined in Config.lb. */
struct southbridge_amd_rs690_config
{
u32 vga_rom_address; /* The location that the VGA rom has been appened. */
u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */