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soc/mediatek: Add support for input 1P mode of dp_intf 

MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Rex-BC Chen 2022-10-13 14:24:09 +08:00 committed by Yu-Ping Wu
parent 319fce53c8
commit d641addf38
4 changed files with 47 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
src/soc/mediatek/common/dp/dp_intf.c
View File

@ -9,22 +9,22 @@
#include <soc/pll_common.h> #include <soc/pll_common.h>
#include <soc/spm.h> #include <soc/spm.h>
static void mtk_dpintf_mask(struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask) static void mtk_dpintf_mask(const struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask)
{ {
clrsetbits32(dpintf->regs + offset, mask, val); clrsetbits32(dpintf->regs + offset, mask, val);
} }
static void mtk_dpintf_sw_reset(struct mtk_dpintf *dpintf, bool reset) static void mtk_dpintf_sw_reset(const struct mtk_dpintf *dpintf, bool reset)
{ {
mtk_dpintf_mask(dpintf, DPINTF_RET, reset ? RST : 0, RST); mtk_dpintf_mask(dpintf, DPINTF_RET, reset ? RST : 0, RST);
} }
static void mtk_dpintf_enable(struct mtk_dpintf *dpintf) static void mtk_dpintf_enable(const struct mtk_dpintf *dpintf)
{ {
mtk_dpintf_mask(dpintf, DPINTF_EN, EN, EN); mtk_dpintf_mask(dpintf, DPINTF_EN, EN, EN);
} }
static void mtk_dpintf_config_hsync(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_hsync(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync) struct mtk_dpintf_sync_param *sync)
{ {
mtk_dpintf_mask(dpintf, DPINTF_TGEN_HWIDTH, mtk_dpintf_mask(dpintf, DPINTF_TGEN_HWIDTH,
@ -35,7 +35,7 @@ static void mtk_dpintf_config_hsync(struct mtk_dpintf *dpintf,
sync->front_porch << HFP, HFP_MASK); sync->front_porch << HFP, HFP_MASK);
} }
static void mtk_dpintf_config_vsync(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_vsync(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync, struct mtk_dpintf_sync_param *sync,
u32 width_addr, u32 porch_addr) u32 width_addr, u32 porch_addr)
{ {
@ -53,35 +53,35 @@ static void mtk_dpintf_config_vsync(struct mtk_dpintf *dpintf,
VSYNC_FRONT_PORCH_MASK); VSYNC_FRONT_PORCH_MASK);
} }
static void mtk_dpintf_config_vsync_lodd(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_vsync_lodd(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync) struct mtk_dpintf_sync_param *sync)
{ {
mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH, mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH,
DPINTF_TGEN_VPORCH); DPINTF_TGEN_VPORCH);
} }
static void mtk_dpintf_config_vsync_leven(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_vsync_leven(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync) struct mtk_dpintf_sync_param *sync)
{ {
mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_LEVEN, mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_LEVEN,
DPINTF_TGEN_VPORCH_LEVEN); DPINTF_TGEN_VPORCH_LEVEN);
} }
static void mtk_dpintf_config_vsync_rodd(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_vsync_rodd(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync) struct mtk_dpintf_sync_param *sync)
{ {
mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_RODD, mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_RODD,
DPINTF_TGEN_VPORCH_RODD); DPINTF_TGEN_VPORCH_RODD);
} }
static void mtk_dpintf_config_vsync_reven(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_vsync_reven(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_sync_param *sync) struct mtk_dpintf_sync_param *sync)
{ {
mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_REVEN, mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_REVEN,
DPINTF_TGEN_VPORCH_REVEN); DPINTF_TGEN_VPORCH_REVEN);
} }
static void mtk_dpintf_config_pol(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_pol(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_polarities *dpintf_pol) struct mtk_dpintf_polarities *dpintf_pol)
{ {
u32 pol; u32 pol;
@ -91,24 +91,24 @@ static void mtk_dpintf_config_pol(struct mtk_dpintf *dpintf,
mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, pol, HSYNC_POL | VSYNC_POL); mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, pol, HSYNC_POL | VSYNC_POL);
} }
static void mtk_dpintf_config_3d(struct mtk_dpintf *dpintf, bool en_3d) static void mtk_dpintf_config_3d(const struct mtk_dpintf *dpintf, bool en_3d)
{ {
mtk_dpintf_mask(dpintf, DPINTF_CON, en_3d ? TDFP_EN : 0, TDFP_EN); mtk_dpintf_mask(dpintf, DPINTF_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
} }
static void mtk_dpintf_config_interface(struct mtk_dpintf *dpintf, bool inter) static void mtk_dpintf_config_interface(const struct mtk_dpintf *dpintf, bool inter)
{ {
mtk_dpintf_mask(dpintf, DPINTF_CON, inter ? INTL_EN : 0, INTL_EN); mtk_dpintf_mask(dpintf, DPINTF_CON, inter ? INTL_EN : 0, INTL_EN);
} }
static void mtk_dpintf_config_fb_size(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_fb_size(const struct mtk_dpintf *dpintf,
u32 width, u32 height) u32 width, u32 height)
{ {
mtk_dpintf_mask(dpintf, DPINTF_SIZE, width << HSIZE, HSIZE_MASK); mtk_dpintf_mask(dpintf, DPINTF_SIZE, width << HSIZE, HSIZE_MASK);
mtk_dpintf_mask(dpintf, DPINTF_SIZE, height << VSIZE, VSIZE_MASK); mtk_dpintf_mask(dpintf, DPINTF_SIZE, height << VSIZE, VSIZE_MASK);
} }
static void mtk_dpintf_config_channel_limit(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_channel_limit(const struct mtk_dpintf *dpintf,
struct mtk_dpintf_yc_limit *limit) struct mtk_dpintf_yc_limit *limit)
{ {
mtk_dpintf_mask(dpintf, DPINTF_Y_LIMIT, mtk_dpintf_mask(dpintf, DPINTF_Y_LIMIT,
@ -121,7 +121,7 @@ static void mtk_dpintf_config_channel_limit(struct mtk_dpintf *dpintf,
limit->c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); limit->c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK);
} }
static void mtk_dpintf_config_bit_num(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_bit_num(const struct mtk_dpintf *dpintf,
enum mtk_dpintf_out_bit_num num) enum mtk_dpintf_out_bit_num num)
{ {
u32 val; u32 val;
@ -146,7 +146,7 @@ static void mtk_dpintf_config_bit_num(struct mtk_dpintf *dpintf,
mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, OUT_BIT_MASK); mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, OUT_BIT_MASK);
} }
static void mtk_dpintf_config_channel_swap(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_channel_swap(const struct mtk_dpintf *dpintf,
enum mtk_dpintf_out_channel_swap swap) enum mtk_dpintf_out_channel_swap swap)
{ {
u32 val; u32 val;
@ -178,12 +178,12 @@ static void mtk_dpintf_config_channel_swap(struct mtk_dpintf *dpintf,
mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, CH_SWAP_MASK); mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, CH_SWAP_MASK);
} }
static void mtk_dpintf_config_yuv422_enable(struct mtk_dpintf *dpintf, bool enable) static void mtk_dpintf_config_yuv422_enable(const struct mtk_dpintf *dpintf, bool enable)
{ {
mtk_dpintf_mask(dpintf, DPINTF_CON, enable ? YUV422_EN : 0, YUV422_EN); mtk_dpintf_mask(dpintf, DPINTF_CON, enable ? YUV422_EN : 0, YUV422_EN);
} }
static void mtk_dpintf_config_color_format(struct mtk_dpintf *dpintf, static void mtk_dpintf_config_color_format(const struct mtk_dpintf *dpintf,
enum mtk_dpintf_out_color_format format) enum mtk_dpintf_out_color_format format)
{ {
bool enable; bool enable;
@ -206,7 +206,7 @@ static void mtk_dpintf_config_color_format(struct mtk_dpintf *dpintf,
mtk_dpintf_config_channel_swap(dpintf, channel_swap); mtk_dpintf_config_channel_swap(dpintf, channel_swap);
} }
static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edid) static int mtk_dpintf_power_on(const struct mtk_dpintf *dpintf, const struct edid *edid)
{ {
u32 clksrc; u32 clksrc;
u32 pll_rate; u32 pll_rate;
@ -228,7 +228,7 @@ static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edi
return 0; return 0;
} }
static int mtk_dpintf_set_display_mode(struct mtk_dpintf *dpintf, static int mtk_dpintf_set_display_mode(const struct mtk_dpintf *dpintf,
const struct edid *edid) const struct edid *edid)
{ {
struct mtk_dpintf_yc_limit limit; struct mtk_dpintf_yc_limit limit;
@ -284,7 +284,7 @@ static int mtk_dpintf_set_display_mode(struct mtk_dpintf *dpintf,
mtk_dpintf_config_channel_swap(dpintf, dpintf->channel_swap); mtk_dpintf_config_channel_swap(dpintf, dpintf->channel_swap);
mtk_dpintf_config_color_format(dpintf, dpintf->color_format); mtk_dpintf_config_color_format(dpintf, dpintf->color_format);
mtk_dpintf_mask(dpintf, DPINTF_CON, INPUT_2P_EN, INPUT_2P_EN); mtk_dpintf_mask(dpintf, DPINTF_CON, dpintf->input_mode, INPUT_2P_EN);
mtk_dpintf_sw_reset(dpintf, false); mtk_dpintf_sw_reset(dpintf, false);
return 0; return 0;
@ -292,14 +292,8 @@ static int mtk_dpintf_set_display_mode(struct mtk_dpintf *dpintf,
void dp_intf_config(const struct edid *edid) void dp_intf_config(const struct edid *edid)
{ {
struct mtk_dpintf dpintf = { const struct mtk_dpintf *data = &dpintf_data;
.regs = (void *)(DP_INTF0_BASE),
.color_format = MTK_DPINTF_COLOR_FORMAT_RGB,
.yc_map = MTK_DPINTF_OUT_YC_MAP_RGB,
.bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS,
.channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
};
mtk_dpintf_power_on(&dpintf, edid); mtk_dpintf_power_on(data, edid);
mtk_dpintf_set_display_mode(&dpintf, edid); mtk_dpintf_set_display_mode(data, edid);
} }

9
src/soc/mediatek/common/dp/include/soc/dp_intf.h
View File

@ -4,6 +4,7 @@
#define SOC_MEDIATEK_COMMON_DP_DP_INTF_H #define SOC_MEDIATEK_COMMON_DP_DP_INTF_H
#include <edid.h> #include <edid.h>
#include <types.h>
#define DPINTF_EN 0x00 #define DPINTF_EN 0x00
#define EN BIT(0) #define EN BIT(0)
@ -211,6 +212,11 @@ enum mtk_dpintf_out_color_format {
MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL, MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL,
}; };
enum mtk_dpintf_input_mode {
MTK_DPINTF_INPUT_MODE_1P = 0,
MTK_DPINTF_INPUT_MODE_2P = INPUT_2P_EN,
};
enum TVDPLL_CLK { enum TVDPLL_CLK {
TVDPLL_PLL = 0, TVDPLL_PLL = 0,
TVDPLL_D2 = 1, TVDPLL_D2 = 1,
@ -225,6 +231,7 @@ struct mtk_dpintf {
enum mtk_dpintf_out_yc_map yc_map; enum mtk_dpintf_out_yc_map yc_map;
enum mtk_dpintf_out_bit_num bit_num; enum mtk_dpintf_out_bit_num bit_num;
enum mtk_dpintf_out_channel_swap channel_swap; enum mtk_dpintf_out_channel_swap channel_swap;
enum mtk_dpintf_input_mode input_mode;
}; };
enum mtk_dpintf_polarity { enum mtk_dpintf_polarity {
@ -253,6 +260,8 @@ struct mtk_dpintf_yc_limit {
u16 c_bottom; u16 c_bottom;
}; };
extern const struct mtk_dpintf dpintf_data;
void dp_intf_config(const struct edid *edid); void dp_intf_config(const struct edid *edid);
#endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */ #endif /* SOC_MEDIATEK_COMMON_DP_DP_INTF_H */

2
src/soc/mediatek/mt8195/Makefile.inc
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@ -46,7 +46,7 @@ ramstage-y += ../common/devapc.c devapc.c
ramstage-y += ../common/dfd.c ramstage-y += ../common/dfd.c
ramstage-y += ../common/dpm.c ramstage-y += ../common/dpm.c
ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
ramstage-y += emi.c ramstage-y += emi.c
ramstage-y += hdmi.c ramstage-y += hdmi.c
ramstage-y += ../common/mcu.c ramstage-y += ../common/mcu.c

13
src/soc/mediatek/mt8195/dp_intf.c Normal file
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@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/addressmap.h>
#include <soc/dp_intf.h>
const struct mtk_dpintf dpintf_data = {
.regs = (void *)(DP_INTF0_BASE),
.color_format = MTK_DPINTF_COLOR_FORMAT_RGB,
.yc_map = MTK_DPINTF_OUT_YC_MAP_RGB,
.bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS,
.channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
.input_mode = MTK_DPINTF_INPUT_MODE_2P,
};