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mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake U 

Coffeelake U has 32MB flash chip support. Adding fmd file and enabling
CFL U board's Kconfig to output 32MB rom file.

Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This commit is contained in:
Maulik V Vaghela 2018-08-07 14:26:04 +05:30 committed by Patrick Georgi
parent dfc9917080
commit d64b940801
2 changed files with 51 additions and 1 deletions
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9
src/mainboard/intel/coffeelake_rvp/Kconfig
View File

@ -2,7 +2,8 @@ if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COFFEELAKE_RVP11
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU
select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
@ -41,6 +42,12 @@ config DEVICETREE
string string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config FMDFILE
string
depends on VBOOT
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_16384
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos_32MB.fmd" if BOARD_ROMSIZE_KB_32768
config INCLUDE_SND_MAX98357_DA7219_NHLT config INCLUDE_SND_MAX98357_DA7219_NHLT
bool "Include blobs for audio with MAX98357_DA7219" bool "Include blobs for audio with MAX98357_DA7219"
select DRIVERS_GENERIC_MAX98357A select DRIVERS_GENERIC_MAX98357A

43
src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd Normal file
View File

@ -0,0 +1,43 @@
FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x1081000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x80000
SI_ME@0x81000 0x1000000
}
SI_BIOS@0x1400000 0xC00000 {
RW_SECTION_A@0x0 0x2d0000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x2bffc0
RW_FWID_A@0x2cffc0 0x40
}
RW_SECTION_B@0x2d0000 0x2d0000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x2bffc0
RW_FWID_B@0x2cffc0 0x40
}
RW_MISC@0x5a0000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000
}
RW_LEGACY(CBFS)@0x5d0000 0x200000
WP_RO@0x7d0000 0x430000 {
RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x42c000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x33c000
}
}
}
}