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A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes: 

- Make get_dsdt script executable.

 - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.

 - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
   is correct.

 - Fix broken or incorrect #include names to increase likelyhood of a
   successful compile.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2009-06-07 14:38:32 +00:00
parent 0ffff3434e
commit d64f403f8e
7 changed files with 151 additions and 131 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/via/epia-m700/Options.lb
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@ -120,7 +120,7 @@ default CONFIG_UDELAY_TSC = 1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
default HAVE_HARD_RESET = 0 default HAVE_HARD_RESET = 0
default HAVE_PIRQ_TABLE = 0 default HAVE_PIRQ_TABLE = 0
default IRQ_SLOT_COUNT = 10 # FIXME. irq_table.c says 14. default IRQ_SLOT_COUNT = 14
default HAVE_ACPI_TABLES = 1 default HAVE_ACPI_TABLES = 1
default HAVE_OPTION_TABLE = 1 default HAVE_OPTION_TABLE = 1
default ROM_IMAGE_SIZE = 128 * 1024 default ROM_IMAGE_SIZE = 128 * 1024

33
src/mainboard/via/epia-m700/cache_as_ram_auto.c
View File

@ -48,12 +48,12 @@
#include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/lapic/boot_cpu.c"
/* This file contains the board-special SI value for raminit.c. */ /* This file contains the board-special SI value for raminit.c. */
#include "mainboard/via/6413e/DrivingClkPhaseData.c" #include "driving_clk_phase_data.c"
#include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.h"
#include "northbridge/via/vx800/raminit.c" #include "northbridge/via/vx800/raminit.c"
#include "cpu/x86/car/copy_and_run.c" #include "cpu/x86/car/copy_and_run.c"
#include "mainboard/via/6413e/wakeup.h" #include "wakeup.h"
/* /*
* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
@ -217,7 +217,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
/* VT3409 no PCI-E */ /* VT3409 no PCI-E */
0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range
0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie
//0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
// Set ROMSIP value by software // Set ROMSIP value by software
/* /*
@ -248,26 +248,27 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)
*/
// CPU Host Bus Control // CPU Host Bus Control
0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
//0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
//0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
//0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
//0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
//0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
// 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
//0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
@ -285,7 +286,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
#define gCom1Base 0x3f8 #define gCom1Base 0x3f8
#define gCom2Base 0x2f8 #define gCom2Base 0x2f8
void EmbedComInit() void EmbedComInit(void)
{ {
u8 ByteVal; u8 ByteVal;
u16 ComBase; u16 ComBase;
@ -351,9 +352,7 @@ void EmbedComInit()
//noharddrive //noharddrive
/* Set embedded COM1 I/O base = 0x3E8 */ /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */
//D17F0RB4
//ByteVal = 0xFD;
if (USE_COM1 == 1) { if (USE_COM1 == 1) {
ByteVal = (u8) ((gCom1Base >> 3) | 0x80); ByteVal = (u8) ((gCom1Base >> 3) | 0x80);
pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal);
@ -362,9 +361,7 @@ void EmbedComInit()
pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
} }
/* Set embedded COM2 I/O base = 0x2E8. */ /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */
//D17F0RB5
//ByteVal = 0xDD;
if (USE_COM2 == 1) { if (USE_COM2 == 1) {
ByteVal = (u8) ((gCom2Base >> 3) | 0x80); ByteVal = (u8) ((gCom2Base >> 3) | 0x80);
pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);

2
src/mainboard/via/epia-m700/DrivingClkPhaseData.c → src/mainboard/via/epia-m700/driving_clk_phase_data.c
View File

@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include "northbridge/via/vx800/DrivingClkPhaseData.h" #include "northbridge/via/vx800/driving_clk_phase_data.h"
// DQS Driving // DQS Driving
// Reg0xE0, 0xE1 // Reg0xE0, 0xE1

2
src/mainboard/via/epia-m700/fadt.c
View File

@ -23,7 +23,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <../../../northbridge/via/vx800/vx800.h> #include <../../../northbridge/via/vx800/vx800.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{ {
acpi_header_t *header = &(fadt->header); acpi_header_t *header = &(fadt->header);

0
src/mainboard/via/epia-m700/get_dsdt Normal file → Executable file
View File

2
src/mainboard/via/epia-m700/irq_tables.c
View File

@ -23,7 +23,7 @@
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32 + 16 * 14, /* There can be total 14 devices on the bus */ 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
0x00, /* Where the interrupt router lies (bus) */ 0x00, /* Where the interrupt router lies (bus) */
(0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */ 0xc20, /* IRQs devoted exclusively to PCI usage */

241
src/mainboard/via/epia-m700/wakeup.c
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@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* reboot.c from Linux. */ /* Parts of this code is taken from reboot.c from Linux. */
/* /*
* This file mostly copied from Rudolf's S3 patch, some changes in * This file mostly copied from Rudolf's S3 patch, some changes in
@ -57,12 +57,12 @@ struct Xgt_desc_struct {
unsigned short pad; unsigned short pad;
} __attribute__ ((packed)); } __attribute__ ((packed));
static struct Xgt_desc_struct static struct Xgt_desc_struct real_mode_gdt = {
real_mode_gdt = sizeof(real_mode_gdt_entries) - 1,
{ sizeof(real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries }, (long)real_mode_gdt_entries
real_mode_idt = { },
0x3ff, 0}, no_idt = { real_mode_idt = {0x3ff, 0},
0, 0}; no_idt = { 0, 0 };
/* /*
* This is 16-bit protected mode code to disable paging and the cache, * This is 16-bit protected mode code to disable paging and the cache,
@ -85,16 +85,16 @@ static struct Xgt_desc_struct
* occurred; hopefully real BIOSs don't assume much. * occurred; hopefully real BIOSs don't assume much.
*/ */
// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ // 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */
static unsigned char real_mode_switch[] = { static unsigned char real_mode_switch[] = {
0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */
0x24, 0xfe, /* andb $0xfe,al */ 0x24, 0xfe, /* andb $0xfe,al */
0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */
}; };
static unsigned char jump_to_wakeup[] = { static unsigned char jump_to_wakeup[] = {
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
}; };
/* /*
@ -103,18 +103,17 @@ static unsigned char jump_to_wakeup[] = {
* We assume that length will aways be less that 100! * We assume that length will aways be less that 100!
*/ */
static unsigned char show31[6] = { static unsigned char show31[6] = {
0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
}; };
static unsigned char show32[6] = { static unsigned char show32[6] = {
0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
}; };
void acpi_jump_wake(u32 vector) void acpi_jump_wake(u32 vector)
{ {
u32 tmp; u32 tmp, dwEip;
u16 tmpvector; u16 tmpvector;
u32 dwEip;
u8 Data; u8 Data;
struct Xgt_desc_struct *wake_thunk16_Xgt_desc; struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
@ -137,7 +136,7 @@ void acpi_jump_wake(u32 vector)
jason_tsc_count_end(); jason_tsc_count_end();
unsigned long long *real_mode_gdt_entries_at_eseg; unsigned long long *real_mode_gdt_entries_at_eseg;
real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0; real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */
real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */ real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */
real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */ real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */
real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */ real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */
@ -150,24 +149,25 @@ void acpi_jump_wake(u32 vector)
wake_thunk16_Xgt_desc[2].size = 0; wake_thunk16_Xgt_desc[2].size = 0;
wake_thunk16_Xgt_desc[2].address = 0; wake_thunk16_Xgt_desc[2].address = 0;
/*added this code to get current value of EIP /* Added this code to get current value of EIP. */
*/ __asm__ volatile (
__asm__ volatile ("calll geip\n\t" "calll geip\n\t"
"geip: \n\t" "popl %0\n\t":"=a" (dwEip) "geip: \n\t"
); "popl %0\n\t"
: "=a" (dwEip)
);
unsigned char *dest; unsigned char *dest, *src;
unsigned char *src;
src = (unsigned char *)dwEip; src = (unsigned char *)dwEip;
dest = WAKE_RECOVER1M_CODE; dest = WAKE_RECOVER1M_CODE;
u32 i; u32 i;
for (i = 0; i < 0x200; i++) for (i = 0; i < 0x200; i++)
dest[i] = src[i]; dest[i] = src[i];
__asm__ __volatile__("ljmp $0x0010,%0" //08 error __asm__ __volatile__("ljmp $0x0010,%0" /* 08 error */
::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20))); ::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20)));
/*added 0x20 "nop" to make sure the ljmp will not jump then halt */ /* Added 0x20 "nop" to make sure the ljmp will not jump then halt. */
asm volatile ("nop"); asm volatile ("nop");
asm volatile ("nop"); asm volatile ("nop");
asm volatile ("nop"); asm volatile ("nop");
@ -202,104 +202,126 @@ void acpi_jump_wake(u32 vector)
asm volatile ("nop"); asm volatile ("nop");
__asm__ volatile ( __asm__ volatile (
/* set new esp, maybe ebp should not equal to esp?, /*
due to the variable in acpi_jump_wake?, anyway, this may be not a big problem. * Set new esp, maybe ebp should not equal to esp?, due to the
and I didnt clear the area (ef000+-0x200) to zero. * variable in acpi_jump_wake?, anyway, this may be not a big
*/ * problem. and I didn't clear the area (ef000+-0x200) to zero.
"movl %0, %%ebp\n\t" */
"movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK) "movl %0, %%ebp\n\t"
); "movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK)
);
/* added this /*
only "src" and "dest" use the new stack, and the esp maybe also used in resumevector * Only "src" and "dest" use the new stack, and the esp maybe also
* used in resumevector.
*/ */
#if PAYLOAD_IS_SEABIOS==1 #if PAYLOAD_IS_SEABIOS == 1
// WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c /* WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c. */
src = src =
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000); (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000);
dest = 0; dest = 0;
for (i = 0; i < 0xa0000; i++) //if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec.
/*
* If recovered 0-e0000, then when resume, before WinXP turn on the
* desktop screen, there is gray background which last 1sec.
*/
for (i = 0; i < 0xa0000; i++)
dest[i] = src[i]; dest[i] = src[i];
/*__asm__ volatile (
"movl %0, %%esi\n\t"
"movl $0, %%edi\n\t"
"movl $0xa0000, %%ecx\n\t"
"shrl $2, %%ecx\n\t"
"rep movsd\n\t"
::"a"(src)
);*/
src =
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
0xc0000);
//dest = 0xc0000;
//for (i = 0; i < 0x20000; i++)
// dest[i] = src[i];
/* __asm__ volatile (
"movl %0, %%esi\n\t"
"movl $0xc0000, %%edi\n\t"
"movl $0x20000, %%ecx\n\t"
"shrl $2, %%ecx\n\t"
"rep movsd\n\t"
::"a"(src)
); */
src = #if 0
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + __asm__ volatile (
0xe0000 + WAKE_SPECIAL_SIZE); "movl %0, %%esi\n\t"
//dest = 0xf0000; "movl $0, %%edi\n\t"
//for (i = 0; i < 0x10000; i++) "movl $0xa0000, %%ecx\n\t"
// dest[i] = src[i]; "shrl $2, %%ecx\n\t"
__asm__ volatile ("movl %0, %%esi\n\t" "rep movsd\n\t"
"movl %1, %%edi\n\t" ::"a"(src)
"movl %2, %%ecx\n\t" );
"shrl $2, %%ecx\n\t" #endif
"rep movsd\n\t"::"r" (src), src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
"r"(0xe0000 + WAKE_SPECIAL_SIZE), - 0x100000 + 0xc0000);
"r"(0x10000 - WAKE_SPECIAL_SIZE)
);
src = #if 0
(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + dest = 0xc0000;
0xf0000); for (i = 0; i < 0x20000; i++)
//dest = 0xf0000; dest[i] = src[i];
//for (i = 0; i < 0x10000; i++)
// dest[i] = src[i]; __asm__ volatile (
__asm__ volatile ("movl %0, %%esi\n\t" "movl %0, %%esi\n\t"
"movl $0xf0000, %%edi\n\t" "movl $0xc0000, %%edi\n\t"
"movl $0x10000, %%ecx\n\t" "movl $0x20000, %%ecx\n\t"
"shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src) "shrl $2, %%ecx\n\t"
); "rep movsd\n\t"
::"a"(src)
);
#endif
src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
- 0x100000 + 0xe0000 + WAKE_SPECIAL_SIZE);
/* dest = 0xf0000; */
/* for (i = 0; i < 0x10000; i++) */
/* dest[i] = src[i]; */
__asm__ volatile (
"movl %0, %%esi\n\t"
"movl %1, %%edi\n\t"
"movl %2, %%ecx\n\t"
"shrl $2, %%ecx\n\t"
"rep movsd\n\t"::"r" (src),
"r"(0xe0000 + WAKE_SPECIAL_SIZE),
"r"(0x10000 - WAKE_SPECIAL_SIZE)
);
src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
- 0x100000 + 0xf0000);
/* dest = 0xf0000; */
/* for (i = 0; i < 0x10000; i++) */
/* dest[i] = src[i]; */
__asm__ volatile (
"movl %0, %%esi\n\t"
"movl $0xf0000, %%edi\n\t"
"movl $0x10000, %%ecx\n\t"
"shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src)
);
asm volatile ("wbinvd"); asm volatile ("wbinvd");
#endif #endif
/* Set up the IDT for real mode. */ /* Set up the IDT for real mode. */
asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1])); asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1]));
/* Set up a GDT from which we can load segment descriptors for real /*
mode. The GDT is not used in real mode; it is just needed here to * Set up a GDT from which we can load segment descriptors for real
prepare the descriptors. */ * mode. The GDT is not used in real mode; it is just needed here to
* prepare the descriptors.
*/
asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0])); asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0]));
/* Load the data segment registers, and thus the descriptors ready for /*
real mode. The base address of each segment is 0x100, 16 times the * Load the data segment registers, and thus the descriptors ready for
selector value being loaded here. This is so that the segment * real mode. The base address of each segment is 0x100, 16 times the
registers don't have to be reloaded after switching to real mode: * selector value being loaded here. This is so that the segment
the values are consistent for real mode operation already. */ * registers don't have to be reloaded after switching to real mode:
* the values are consistent for real mode operation already.
*/
__asm__ __volatile__(
"movl $0x0010,%%eax\n"
"\tmovl %%eax,%%ds\n"
"\tmovl %%eax,%%es\n"
"\tmovl %%eax,%%fs\n"
"\tmovl %%eax,%%gs\n"
"\tmovl %%eax,%%ss":::"eax"
);
__asm__ __volatile__("movl $0x0010,%%eax\n" /*
"\tmovl %%eax,%%ds\n" * Jump to the 16-bit code that we copied earlier. It disables paging
"\tmovl %%eax,%%es\n" * and the cache, switches to real mode, and jumps to the BIOS reset
"\tmovl %%eax,%%fs\n" * entry point.
"\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss":::"eax"); */
/* Jump to the 16-bit code that we copied earlier. It disables paging __asm__ __volatile__(
and the cache, switches to real mode, and jumps to the BIOS reset "ljmp $0x0008,%0"::"i"
entry point. */ ((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100))
);
__asm__
__volatile__("ljmp $0x0008,%0"::"i"
((void *)(WAKE_THUNK16_ADDR -
sizeof(real_mode_switch) - 100)));
} }
/* -*- linux-c -*- ------------------------------------------------------- * /* -*- linux-c -*- ------------------------------------------------------- *
@ -318,7 +340,7 @@ void acpi_jump_wake(u32 vector)
* Enable A20 gate (return -1 on failure) * Enable A20 gate (return -1 on failure)
*/ */
//#include "boot.h" // #include "boot.h"
#define MAX_8042_LOOPS 100000 #define MAX_8042_LOOPS 100000
@ -429,8 +451,9 @@ int enable_a20(void)
/* Try enabling A20 through the keyboard controller */ /* Try enabling A20 through the keyboard controller */
empty_8042(); empty_8042();
//if (a20_test_short())
// return 0; /* BIOS worked, but with delayed reaction */ // if (a20_test_short())
// return 0; /* BIOS worked, but with delayed reaction */
enable_a20_kbc(); enable_a20_kbc();
if (a20_test_long()) if (a20_test_long())