A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes:
- Make get_dsdt script executable. - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c. - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c is correct. - Fix broken or incorrect #include names to increase likelyhood of a successful compile. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
0ffff3434e
commit
d64f403f8e
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@ -120,7 +120,7 @@ default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default HAVE_HARD_RESET = 0
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default HAVE_PIRQ_TABLE = 0
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default IRQ_SLOT_COUNT = 10 # FIXME. irq_table.c says 14.
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default IRQ_SLOT_COUNT = 14
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default HAVE_ACPI_TABLES = 1
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default HAVE_OPTION_TABLE = 1
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default ROM_IMAGE_SIZE = 128 * 1024
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@ -48,12 +48,12 @@
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#include "cpu/x86/lapic/boot_cpu.c"
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/* This file contains the board-special SI value for raminit.c. */
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#include "mainboard/via/6413e/DrivingClkPhaseData.c"
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#include "driving_clk_phase_data.c"
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#include "northbridge/via/vx800/raminit.h"
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#include "northbridge/via/vx800/raminit.c"
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#include "cpu/x86/car/copy_and_run.c"
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#include "mainboard/via/6413e/wakeup.h"
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#include "wakeup.h"
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/*
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* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
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@ -217,7 +217,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
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/* VT3409 no PCI-E */
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0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range
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0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie
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//0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
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// 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control
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// Set ROMSIP value by software
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/*
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@ -248,26 +248,27 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
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0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0)
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0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1)
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0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2)
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0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */
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0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3)
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*/
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// CPU Host Bus Control
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0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
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//0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
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// 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
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0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
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0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance
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//0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
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// 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
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0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
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0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access
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//0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
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// 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2
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0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2
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0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1
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//0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
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//0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
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// 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
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// 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2
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0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy
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0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer
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0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl
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// 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3
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//0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
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// 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2
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0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2
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0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3
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0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4
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@ -285,7 +286,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
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#define gCom1Base 0x3f8
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#define gCom2Base 0x2f8
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void EmbedComInit()
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void EmbedComInit(void)
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{
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u8 ByteVal;
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u16 ComBase;
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@ -351,9 +352,7 @@ void EmbedComInit()
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//noharddrive
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/* Set embedded COM1 I/O base = 0x3E8 */
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//D17F0RB4
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//ByteVal = 0xFD;
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/* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */
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if (USE_COM1 == 1) {
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ByteVal = (u8) ((gCom1Base >> 3) | 0x80);
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pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal);
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@ -362,9 +361,7 @@ void EmbedComInit()
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pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal);
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}
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/* Set embedded COM2 I/O base = 0x2E8. */
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//D17F0RB5
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//ByteVal = 0xDD;
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/* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */
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if (USE_COM2 == 1) {
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ByteVal = (u8) ((gCom2Base >> 3) | 0x80);
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pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal);
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@ -18,7 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "northbridge/via/vx800/DrivingClkPhaseData.h"
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#include "northbridge/via/vx800/driving_clk_phase_data.h"
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// DQS Driving
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// Reg0xE0, 0xE1
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@ -23,7 +23,7 @@
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#include <arch/acpi.h>
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#include <../../../northbridge/via/vx800/vx800.h>
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void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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@ -23,7 +23,7 @@
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * 14, /* There can be total 14 devices on the bus */
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32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0xc20, /* IRQs devoted exclusively to PCI usage */
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@ -19,7 +19,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* reboot.c from Linux. */
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/* Parts of this code is taken from reboot.c from Linux. */
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/*
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* This file mostly copied from Rudolf's S3 patch, some changes in
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@ -57,12 +57,12 @@ struct Xgt_desc_struct {
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unsigned short pad;
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} __attribute__ ((packed));
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static struct Xgt_desc_struct
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real_mode_gdt =
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{ sizeof(real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries },
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real_mode_idt = {
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0x3ff, 0}, no_idt = {
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0, 0};
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static struct Xgt_desc_struct real_mode_gdt = {
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sizeof(real_mode_gdt_entries) - 1,
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(long)real_mode_gdt_entries
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},
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real_mode_idt = {0x3ff, 0},
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no_idt = { 0, 0 };
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/*
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* This is 16-bit protected mode code to disable paging and the cache,
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@ -85,7 +85,7 @@ static struct Xgt_desc_struct
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* occurred; hopefully real BIOSs don't assume much.
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*/
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// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */
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// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */
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static unsigned char real_mode_switch[] = {
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0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */
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@ -103,18 +103,17 @@ static unsigned char jump_to_wakeup[] = {
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* We assume that length will aways be less that 100!
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*/
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static unsigned char show31[6] = {
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0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */
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0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
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};
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static unsigned char show32[6] = {
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0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */
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0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
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};
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void acpi_jump_wake(u32 vector)
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{
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u32 tmp;
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u32 tmp, dwEip;
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u16 tmpvector;
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u32 dwEip;
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u8 Data;
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struct Xgt_desc_struct *wake_thunk16_Xgt_desc;
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@ -137,7 +136,7 @@ void acpi_jump_wake(u32 vector)
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jason_tsc_count_end();
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unsigned long long *real_mode_gdt_entries_at_eseg;
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real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0;
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real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */
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real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */
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real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */
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real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */
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@ -150,24 +149,25 @@ void acpi_jump_wake(u32 vector)
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wake_thunk16_Xgt_desc[2].size = 0;
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wake_thunk16_Xgt_desc[2].address = 0;
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/*added this code to get current value of EIP
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*/
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__asm__ volatile ("calll geip\n\t"
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"geip: \n\t" "popl %0\n\t":"=a" (dwEip)
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/* Added this code to get current value of EIP. */
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__asm__ volatile (
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"calll geip\n\t"
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"geip: \n\t"
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"popl %0\n\t"
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: "=a" (dwEip)
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);
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unsigned char *dest;
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unsigned char *src;
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unsigned char *dest, *src;
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src = (unsigned char *)dwEip;
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dest = WAKE_RECOVER1M_CODE;
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u32 i;
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for (i = 0; i < 0x200; i++)
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dest[i] = src[i];
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__asm__ __volatile__("ljmp $0x0010,%0" //08 error
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__asm__ __volatile__("ljmp $0x0010,%0" /* 08 error */
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::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20)));
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/*added 0x20 "nop" to make sure the ljmp will not jump then halt */
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/* Added 0x20 "nop" to make sure the ljmp will not jump then halt. */
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asm volatile ("nop");
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asm volatile ("nop");
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asm volatile ("nop");
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@ -202,54 +202,68 @@ void acpi_jump_wake(u32 vector)
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asm volatile ("nop");
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__asm__ volatile (
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/* set new esp, maybe ebp should not equal to esp?,
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due to the variable in acpi_jump_wake?, anyway, this may be not a big problem.
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and I didnt clear the area (ef000+-0x200) to zero.
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/*
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* Set new esp, maybe ebp should not equal to esp?, due to the
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* variable in acpi_jump_wake?, anyway, this may be not a big
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* problem. and I didn't clear the area (ef000+-0x200) to zero.
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*/
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"movl %0, %%ebp\n\t"
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"movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK)
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);
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/* added this
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only "src" and "dest" use the new stack, and the esp maybe also used in resumevector
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/*
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* Only "src" and "dest" use the new stack, and the esp maybe also
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* used in resumevector.
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*/
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#if PAYLOAD_IS_SEABIOS==1
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// WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c
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#if PAYLOAD_IS_SEABIOS == 1
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/* WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c. */
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src =
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(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000);
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dest = 0;
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for (i = 0; i < 0xa0000; i++) //if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec.
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/*
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* If recovered 0-e0000, then when resume, before WinXP turn on the
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* desktop screen, there is gray background which last 1sec.
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*/
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for (i = 0; i < 0xa0000; i++)
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dest[i] = src[i];
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/*__asm__ volatile (
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#if 0
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__asm__ volatile (
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"movl %0, %%esi\n\t"
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"movl $0, %%edi\n\t"
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"movl $0xa0000, %%ecx\n\t"
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"shrl $2, %%ecx\n\t"
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"rep movsd\n\t"
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::"a"(src)
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);*/
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src =
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(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
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0xc0000);
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//dest = 0xc0000;
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//for (i = 0; i < 0x20000; i++)
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// dest[i] = src[i];
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/* __asm__ volatile (
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);
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#endif
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src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
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- 0x100000 + 0xc0000);
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#if 0
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dest = 0xc0000;
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for (i = 0; i < 0x20000; i++)
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dest[i] = src[i];
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__asm__ volatile (
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"movl %0, %%esi\n\t"
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"movl $0xc0000, %%edi\n\t"
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"movl $0x20000, %%ecx\n\t"
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"shrl $2, %%ecx\n\t"
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"rep movsd\n\t"
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::"a"(src)
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); */
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);
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#endif
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src =
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(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
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0xe0000 + WAKE_SPECIAL_SIZE);
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//dest = 0xf0000;
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//for (i = 0; i < 0x10000; i++)
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// dest[i] = src[i];
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__asm__ volatile ("movl %0, %%esi\n\t"
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src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
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- 0x100000 + 0xe0000 + WAKE_SPECIAL_SIZE);
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/* dest = 0xf0000; */
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/* for (i = 0; i < 0x10000; i++) */
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/* dest[i] = src[i]; */
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__asm__ volatile (
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"movl %0, %%esi\n\t"
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"movl %1, %%edi\n\t"
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"movl %2, %%ecx\n\t"
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"shrl $2, %%ecx\n\t"
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@ -258,13 +272,13 @@ void acpi_jump_wake(u32 vector)
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"r"(0x10000 - WAKE_SPECIAL_SIZE)
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);
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src =
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(unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 +
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0xf0000);
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//dest = 0xf0000;
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//for (i = 0; i < 0x10000; i++)
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// dest[i] = src[i];
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__asm__ volatile ("movl %0, %%esi\n\t"
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src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024
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- 0x100000 + 0xf0000);
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/* dest = 0xf0000; */
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/* for (i = 0; i < 0x10000; i++) */
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/* dest[i] = src[i]; */
|
||||
__asm__ volatile (
|
||||
"movl %0, %%esi\n\t"
|
||||
"movl $0xf0000, %%edi\n\t"
|
||||
"movl $0x10000, %%ecx\n\t"
|
||||
"shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src)
|
||||
|
|
@ -275,31 +289,39 @@ void acpi_jump_wake(u32 vector)
|
|||
/* Set up the IDT for real mode. */
|
||||
asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1]));
|
||||
|
||||
/* Set up a GDT from which we can load segment descriptors for real
|
||||
mode. The GDT is not used in real mode; it is just needed here to
|
||||
prepare the descriptors. */
|
||||
/*
|
||||
* Set up a GDT from which we can load segment descriptors for real
|
||||
* mode. The GDT is not used in real mode; it is just needed here to
|
||||
* prepare the descriptors.
|
||||
*/
|
||||
asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0]));
|
||||
|
||||
/* Load the data segment registers, and thus the descriptors ready for
|
||||
real mode. The base address of each segment is 0x100, 16 times the
|
||||
selector value being loaded here. This is so that the segment
|
||||
registers don't have to be reloaded after switching to real mode:
|
||||
the values are consistent for real mode operation already. */
|
||||
|
||||
__asm__ __volatile__("movl $0x0010,%%eax\n"
|
||||
/*
|
||||
* Load the data segment registers, and thus the descriptors ready for
|
||||
* real mode. The base address of each segment is 0x100, 16 times the
|
||||
* selector value being loaded here. This is so that the segment
|
||||
* registers don't have to be reloaded after switching to real mode:
|
||||
* the values are consistent for real mode operation already.
|
||||
*/
|
||||
__asm__ __volatile__(
|
||||
"movl $0x0010,%%eax\n"
|
||||
"\tmovl %%eax,%%ds\n"
|
||||
"\tmovl %%eax,%%es\n"
|
||||
"\tmovl %%eax,%%fs\n"
|
||||
"\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss":::"eax");
|
||||
"\tmovl %%eax,%%gs\n"
|
||||
"\tmovl %%eax,%%ss":::"eax"
|
||||
);
|
||||
|
||||
/* Jump to the 16-bit code that we copied earlier. It disables paging
|
||||
and the cache, switches to real mode, and jumps to the BIOS reset
|
||||
entry point. */
|
||||
/*
|
||||
* Jump to the 16-bit code that we copied earlier. It disables paging
|
||||
* and the cache, switches to real mode, and jumps to the BIOS reset
|
||||
* entry point.
|
||||
*/
|
||||
|
||||
__asm__
|
||||
__volatile__("ljmp $0x0008,%0"::"i"
|
||||
((void *)(WAKE_THUNK16_ADDR -
|
||||
sizeof(real_mode_switch) - 100)));
|
||||
__asm__ __volatile__(
|
||||
"ljmp $0x0008,%0"::"i"
|
||||
((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100))
|
||||
);
|
||||
}
|
||||
|
||||
/* -*- linux-c -*- ------------------------------------------------------- *
|
||||
|
|
@ -318,7 +340,7 @@ void acpi_jump_wake(u32 vector)
|
|||
* Enable A20 gate (return -1 on failure)
|
||||
*/
|
||||
|
||||
//#include "boot.h"
|
||||
// #include "boot.h"
|
||||
|
||||
#define MAX_8042_LOOPS 100000
|
||||
|
||||
|
|
@ -429,8 +451,9 @@ int enable_a20(void)
|
|||
|
||||
/* Try enabling A20 through the keyboard controller */
|
||||
empty_8042();
|
||||
//if (a20_test_short())
|
||||
// return 0; /* BIOS worked, but with delayed reaction */
|
||||
|
||||
// if (a20_test_short())
|
||||
// return 0; /* BIOS worked, but with delayed reaction */
|
||||
|
||||
enable_a20_kbc();
|
||||
if (a20_test_long())
|
||||
|
|
|
|||
Loading…
Reference in New Issue