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kunimitsu: Enable wake-on-wifi 

- Assign GPE DW0 to GPP_B block
- Enable GPP_B16 as ACPI_SCI for wake
- Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW

Note that current designs cannot wake from Deep S3 via wifi.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot

Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529
Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2015-09-08 16:28:21 -07:00 committed by Patrick Georgi
parent e09eb68088
commit d6a42f9af8
3 changed files with 19 additions and 3 deletions
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13
src/mainboard/intel/kunimitsu/acpi/mainboard.asl
View File

@ -58,6 +58,19 @@ Scope (\_SB.PCI0.LPCB)
#include <drivers/pc80/tpm/acpi/tpm.asl> #include <drivers/pc80/tpm/acpi/tpm.asl>
} }
/*
* WLAN connected to Root Port 1
*/
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
{
Name (_ADR, 0x00000000)
Name (_DDR, "Wireless LAN")
Name (_PRW, Package () { GPE_WLAN_WAKE, 3 })
}
}
Scope (\_SB.PCI0.I2C0) Scope (\_SB.PCI0.I2C0)
{ {
/* Touchscreen */ /* Touchscreen */

2
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -9,7 +9,7 @@ chip soc/intel/skylake
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE # route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed. # offset bits also need to be changed.
register "gpe0_dw0" = "GPP_C" register "gpe0_dw0" = "GPP_B"
register "gpe0_dw1" = "GPP_D" register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E" register "gpe0_dw2" = "GPP_E"

7
src/mainboard/intel/kunimitsu/gpio.h
View File

@ -39,12 +39,15 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK #define GPE_EC_WAKE GPE0_LAN_WAK
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
#define GPE_WLAN_WAKE GPE0_DW0_16
/* Input device interrupt configuration */ /* Input device interrupt configuration */
#define TOUCHPAD_INT_L GPP_B3_IRQ #define TOUCHPAD_INT_L GPP_B3_IRQ
#define TOUCHSCREEN_INT_L GPP_E7_IRQ #define TOUCHSCREEN_INT_L GPP_E7_IRQ
#define MIC_INT_L GPP_F10_IRQ #define MIC_INT_L GPP_F10_IRQ
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
#define EC_SCI_GPI GPE0_DW2_16 #define EC_SCI_GPI GPE0_DW2_16
#define EC_SMI_GPI GPP_E15 #define EC_SMI_GPI GPP_E15
@ -91,7 +94,7 @@ static const struct pad_config gpio_table[] = {
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), /* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ /* GPP_B15 */ /* GSPI0_CS# */ /* GPP_B15 */
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
/* GSPI0_MOSI */ /* GPP_B18 */ /* GSPI0_MOSI */ /* GPP_B18 */
/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),