gizmosphere/gizmo2: Changes to make it gizmo2

The preceding patch copied gizmo2 from the amd/olivehill
board. This commit includes the changes required to make
the code reflect the gizmo2 hardware:
  - Update the vendor Kconfig to add gizmo2
  - Update the mainboard Kconfig
  - Update devicetree
  - Add support in for the soldered down DDR3
  - Update the CODEC verb data
  - Update the graphics connector settings
  - Adjust the temperature thresholds for the fan

What's missing:
  - Interrupt routing tables

Gizmo2 can boot DOS and Ubuntu 14.10.

Change-Id: I3d7202957c082974689f2a8c04d8cd33dbdc1a89
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7722
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/mainboard/gizmosphere/Kconfig

@@ -25,9 +25,13 @@ choice
 config BOARD_GIZMOSPHERE_GIZMO
 	bool "Gizmo"
 
+config BOARD_GIZMOSPHERE_GIZMO2
+	bool "Gizmo2"
+
 endchoice
 
 source "src/mainboard/gizmosphere/gizmo/Kconfig"
+source "src/mainboard/gizmosphere/gizmo2/Kconfig"
 
 config MAINBOARD_VENDOR
 	string

src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c

@@ -38,7 +38,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 	{AGESA_DEALLOCATE_BUFFER,        agesa_DeallocateBuffer },
 	{AGESA_LOCATE_BUFFER,            agesa_LocateBuffer },
 	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
+	{AGESA_READ_SPD,                 agesa_ReadSpd_from_cbfs },
 	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
 	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
 	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
@@ -50,29 +50,29 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /**
- * AMD Olivehill Platform ALC272 Verb Table
+ * ALC272 Verb Table
  */
-static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
+const CODEC_ENTRY Alc272_VerbTbl[] = {
 	{0x11, 0x411111F0}, //        - SPDIF_OUT2
 	{0x12, 0x411111F0}, //        - DMIC_1/2
 	{0x13, 0x411111F0}, //        - DMIC_3/4
 	{0x14, 0x411111F0}, // Port D - LOUT1
-	{0x15, 0x411111F0}, // Port A - LOUT2
+	{0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC
 	{0x16, 0x411111F0}, //
 	{0x17, 0x411111F0}, // Port H - MONO
-	{0x18, 0x01a19840}, // Port B - MIC1
+	{0x18, 0x01a11840}, // Port B - MIC1
 	{0x19, 0x411111F0}, // Port F - MIC2
-	{0x1a, 0x01813030}, // Port C - LINE1
+	{0x1a, 0x01811030}, // Port C - LINE1
-	{0x1b, 0x411111F0}, // Port E - LINE2
+	{0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC
 	{0x1d, 0x40130605}, //        - PCBEEP
-	{0x1e, 0x01441120}, //        - SPDIF_OUT1
+	{0x1e, 0x411111F0}, //        - SPDIF_OUT1
-	{0x21, 0x01214010}, // Port I - HPOUT
+	{0x21, 0x01211010}, // Port I - HPOUT
 	{0xff, 0xffffffff}
 };
 
-static const CODEC_TBL_LIST OlivehillCodecTableList[] =
+static const CODEC_TBL_LIST CodecTableList[] =
 {
-	{0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
+	{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
 	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
 };
 
@@ -108,7 +108,7 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] =
 #define FREQ_14HZ			0xFE
 #define FREQ_11HZ			0xFF
 
-/* Olivehill Hardware Monitor Fan Control
+/*  Hardware Monitor Fan Control
  * Hardware limitation:
  *  HWM failed to read the input temperture vi I2C,
  *  if other software switch the I2C switch by mistake or intention.
@@ -146,9 +146,9 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
 	/* IMC Fan Policy temperature thresholds */
 	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
 	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00;	/* Zone */
-	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80;	/*AC0 threshold in Celsius */
+	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 =   50;	/*AC0 threshold in Celsius */
-	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c;	/*AC1 threshold in Celsius */
+	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 =   45;	/*AC1 threshold in Celsius */
-	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32;	/*AC2 threshold in Celsius */
+	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 =   40;	/*AC2 threshold in Celsius */
 	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff;	/*AC3 threshold in Celsius, 0xFF is not define */
 	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff;	/*AC4 threshold in Celsius, 0xFF is not define */
 	FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff;	/*AC5 threshold in Celsius, 0xFF is not define */
@@ -160,9 +160,9 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
 	/* IMC Fan Policy PWM Settings */
 	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
 	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00;	/* Zone */
-	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a;	/* AL0 percentage */
+	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 =  100;	/* AL0 percentage */
-	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46;	/* AL1 percentage */
+	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 =   99;	/* AL1 percentage */
-	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28;	/* AL2 percentage */
+	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 =   98;	/* AL2 percentage */
 	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff;	/* AL3 percentage */
 	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff;	/* AL4 percentage */
 	FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff;	/* AL5 percentage */
@@ -206,7 +206,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
 		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
 
 		/* Azalia Controller OEM Codec Table Pointer */
-		FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
+		FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
 		/* Azalia Controller Front Panel OEM Table Pointer */
 
 		/* Fan Control */

src/mainboard/gizmosphere/gizmo2/Kconfig

@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2013-2014 Sage Electronic Engineering
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,7 +18,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 #
 
-if BOARD_AMD_OLIVEHILL
+if BOARD_GIZMOSPHERE_GIZMO2
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -31,14 +32,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
 	select GFXUMA
+	select SPD_CACHE
 
 config MAINBOARD_DIR
 	string
-	default amd/olivehill
+	default gizmosphere/gizmo2
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "DB-FT3"
+	default "Gizmo2"
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -56,10 +58,6 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
-config ACPI_SSDTX_NUM
-	int
-	default 0
-
 config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
@@ -68,4 +66,4 @@ config HUDSON_LEGACY_FREE
 	bool
 	default y
 
-endif # BOARD_AMD_OLIVEHILL
+endif # BOARD_GIZMOSPHERE_GIZMO2

src/mainboard/gizmosphere/gizmo2/Makefile.inc

@@ -2,6 +2,7 @@
 # This file is part of the coreboot project.
 #
 # Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2014 Sage Electronic Engineering, LLC
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -24,3 +25,23 @@ romstage-y += PlatformGnbPcie.c
 ramstage-y += buildOpts.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
+
+## DIMM SPD for on-board memory
+SPD_BIN = $(obj)/spd.bin
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES  = Micron_MT41J128M16JT
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do echo -e -n "\\x$$c"; \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab

src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex

@@ -0,0 +1,235 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA	02110-1301 USA
+
+# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips
+# The datasheet is available at:
+# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf
+
+#	SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down
+
+#	0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+#		bits[3:0]: 1 = 128 SPD Bytes Used
+#		bits[6:4]: 1 = 256 SPD Bytes Total
+#		bit7     : 0 = CRC covers bytes 0 ~ 125
+11
+
+#	1 SPD Revision -
+#		0x10 = Revision 1.0
+10
+
+#	2 Key Byte / DRAM Device Type
+#		bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+#	3 Key Byte / Module Type
+#		bits[3:0]: 3 = SO-DIMM
+#		bits[7:4]:     reserved
+03
+
+#	4 SDRAM CHIP Density and Banks
+#		bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+#		bits[6:4]: 0 = 3 (8 banks)
+#		bit7     :     reserved
+03
+
+#	5 SDRAM Addressing
+#		bits[2:0]: 1 = 10 Column Address Bits
+#		bits[5:3]: 2 = 14 Row Address Bits
+#		bits[7:6]:     reserved
+11
+
+#	6 Module Nominal Voltage, VDD
+#		bit0     : 0 = 1.5 V operable
+#		bit1     : 0 = NOT 1.35 V operable
+#		bit2     : 0 = NOT 1.25 V operable
+#		bits[7:3]:     reserved
+00
+
+#	7 Module Organization
+#		bits[2:0]: 2 = 16 bits
+#		bits[5:3]: 0 = 1 Rank
+#		bits[7:6]:     reserved
+02
+
+#	8 Module Memory Bus Width
+#		bits[2:0]: 3 = Primary bus width is 64 bits
+#		bits[4:3]: 0 = 0 bits (no bus width extension)
+#		bits[7:5]:     reserved
+03
+
+#	9 Fine Timebase (FTB) Dividend / Divisor
+#		bits[3:0]: 0x02 divisor
+#		bits[7:4]: 0x05 dividend
+#		5/2 = 2.5ps
+52
+
+#	10 Medium Timebase (MTB) Dividend
+#	11 Medium Timebase (MTB) Divisor
+#		1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
+01 08
+
+#	12 SDRAM Minimum Cycle Time (tCKmin)
+#		0x0a  = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
+0A
+
+#	13 Reserved
+00
+
+#	14 CAS Latencies Supported, Least Significant Byte
+#	15 CAS Latencies Supported, Most Significant Byte
+#		Cas Latencies of 11 - 5 are supported
+FE 00
+
+#	16 Minimum CAS Latency Time (tAAmin)
+#		0x6E = 13.75ns - DDR3-1600K
+6E
+
+#	17 Minimum Write Recovery Time (tWRmin)
+#		0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+#	18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+#		0x6E = 13.75ns -  DDR3-1600K
+6E
+
+#	19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+#		0x3C = 7.5ns
+3C
+
+#	20 Minimum Row Precharge Delay Time (tRPmin)
+#		0x6E = 13.75ns -  DDR3-1600K
+6E
+
+#	21 Upper Nibbles for tRAS and tRC
+#		bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+#		bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+#	22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+#		0x118 = 35ns - DDR3-1600 (see byte 21)
+18
+
+#	23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+#		0x186 = 48.75ns - DDR3-1600K
+86
+
+#	24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+#	25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+#		0x500 = 160ns - for 2 Gigabit chips
+00 05
+
+#	26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+#		0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+#	27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+#		0x3c =  7.5ns -  All DDR3 SDRAM speed bins
+3C
+
+#	28 Upper Nibble for tFAWmin
+#	29 Minimum Four Activate Window Delay Time (tFAWmin)
+#		0x0140 = 40ns -  DDR3-1600, 2 KB page size
+01 40
+
+#	30 SDRAM Optional Feature
+#		bit0     : 1= RZQ/6 supported
+#		bit1     : 1 = RZQ/7 supported
+#		bits[6:2]:     reserved
+#		bit7     : 1 = DLL Off mode supported
+83
+
+#	31 SDRAM Thermal and Refresh Options
+#		bit0     : 1 = Temp up to 95c supported
+#		bit1     : 0 = 85-95c uses 2x refresh rate
+#		bit2     : 1 = Auto Self Refresh supported
+#		bit3     : 0 = no on die thermal sensor
+#		bits[6:4]:     reserved
+#		bit7     : 0 = partial self refresh supported
+05
+
+#	32 Module Thermal Sensor
+#		0 = Thermal sensor not incorporated onto this assembly
+00
+
+#	33 SDRAM Device Type
+#		bits[1:0]: 0 = Signal Loading not specified
+#		bits[3:2]:     reserved
+#		bits[6:4]: 0 = Die count not specified
+#		bit7     : 0 = Standard Monolithic DRAM Device
+00
+
+#	34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+#	35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+#	36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+#	37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+#	38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+#	39 - 59 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+#	60 Raw Card Extension, Module Nominal Height
+#		bits[4:0]: 0 = <= 15mm tall
+#		bits[7:5]: 0 = raw card revision 0-3
+00
+
+#	61 Module Maximum Thickness
+#		bits[3:0]: 0 = thickness front <= 1mm
+#		bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+#	62 Reference Raw Card Used
+#		bits[4:0]: 0 = Reference Raw card A used
+#		bits[6:5]: 0 = revision 0
+#		bit7     : 0 = Reference raw cards A through AL
+00
+
+#	63 Address Mapping from Edge Connector to DRAM
+#		bit0     : 0 = standard mapping (not mirrored)
+#		bits[7:1]:     reserved
+00
+
+#	64 - 116 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+#	117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+#		0x0001 = AMD
+00 01
+
+#	119 Module ID: Module Manufacturing Location - oem specified
+#	120 Module ID: Module Manufacture Year in BCD
+#		0x13 = 2013
+00 13
+
+#	121 Module ID: Module Manufacture week
+#		0x12 = 12th week
+12
+
+#	122 - 125: Module Serial Number
+53 41 47 45
+
+#	126 - 127: Cyclical Redundancy Code
+00 00

src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c

@@ -84,19 +84,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
 	{
 		0,
 		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
 	},
-	/* DP1 to FCH */
+	/* DP1 to high-speed edge connector */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DP2 to HDMI1/DP */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
+		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
 	},
 };
 

src/mainboard/gizmosphere/gizmo2/acpi/usb_oc.asl

@@ -41,7 +41,7 @@ Name(UOM9, 6)
 
 /* USB Overcurrent GPEs */
 
-#if 0 /* TODO: Update for Olivehill */
+#if 0 /* TODO: Update */
 Method(UCOC, 0) {
 	Sleep(20)
 	Store(0x13,CMTI)

src/mainboard/gizmosphere/gizmo2/buildOpts.c

@@ -346,11 +346,11 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
 #define DFLT_FCH_GPP_PORT3_HOTPLUG          FALSE
 //#define BLDCFG_IR_PIN_CONTROL	0x33
 
-GPIO_CONTROL   olivehill_gpio[] = {
+GPIO_CONTROL   gizmo2_gpio[] = {
 	{183, Function1, GpioIn | GpioOutEnB | PullUpB},
 	{-1}
 };
-//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&olivehill_gpio[0])
+//#define BLDCFG_FCH_GPIO_CONTROL_LIST           (&gizmo2_gpio[0])
 
 // The following definitions specify the default values for various parameters in which there are
 // no clearly defined defaults to be used in the common file.  The values below are based on product
@@ -437,17 +437,24 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   //      Byte6Seed, Byte7Seed, ByteEccSeed)
   //      Speicifes the HW RXEN training seed for a channel of a socket
   //
+
+	#define SEED_WL 0x0E
+	WRITE_LEVELING_SEED(
+		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+		SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
+		SEED_WL),
+
 	#define SEED_A 0x12
 	HW_RXEN_SEED(
 		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
 		SEED_A),
 
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
-  MOTHER_BOARD_LAYERS (LAYERS_4),
+  MOTHER_BOARD_LAYERS (LAYERS_6),
 
-  MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
+  MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
   CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
   ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
   CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),

src/mainboard/gizmosphere/gizmo2/devicetree.cb

@@ -29,14 +29,14 @@ chip northbridge/amd/agesa/family16kb/root_complex
 
 			chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
 				device pci 0.0 on  end # Root Complex
-				device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x9835
 				device pci 1.1 on  end # Internal Multimedia
 				device pci 2.0 on  end # PCIe Host Bridge
-				device pci 2.1 on  end # x4 PCIe slot
+				device pci 2.1 on  end # PCIe GFX Bridge
-				device pci 2.2 on  end # mPCIe slot
+				device pci 2.2 on  end # PCIe GPP mini PCIe
-				device pci 2.3 on  end # Realtek NIC
+				device pci 2.3 on  end # PCIe LAN
-				device pci 2.4 on  end # Edge Connector
+				device pci 2.4 on  end # PCIe x2 to high speed edge connector
-				device pci 2.5 on  end # Edge Connector
+				device pci 2.5 on  end # PCIe x2 to high speed edge connector
 			end	#chip northbridge/amd/agesa/family16kb
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
@@ -46,14 +46,7 @@ chip northbridge/amd/agesa/family16kb/root_complex
 				device pci 12.2 on  end # USB
 				device pci 13.0 on  end # USB
 				device pci 13.2 on  end # USB
-				device pci 14.0 on      # SM
+				device pci 14.0 on  end # SM
-					chip drivers/generic/generic #dimm 0-0-0
-						device i2c 50 on end
-					end
-					chip drivers/generic/generic #dimm 0-0-1
-						device i2c 51 on end
-					end
-				end # SM
 				device pci 14.2 on  end # HDA	0x4383
 				device pci 14.3 on  end # LPC	0x439d
 				device pci 14.7 on  end # SD
@@ -65,11 +58,6 @@ chip northbridge/amd/agesa/family16kb/root_complex
 			device pci 18.3 on  end
 			device pci 18.4 on  end
 			device pci 18.5 on  end
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
 
 		end	#chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
 	end	#domain