gizmosphere/gizmo2: Changes to make it gizmo2
The preceding patch copied gizmo2 from the amd/olivehill board. This commit includes the changes required to make the code reflect the gizmo2 hardware: - Update the vendor Kconfig to add gizmo2 - Update the mainboard Kconfig - Update devicetree - Add support in for the soldered down DDR3 - Update the CODEC verb data - Update the graphics connector settings - Adjust the temperature thresholds for the fan What's missing: - Interrupt routing tables Gizmo2 can boot DOS and Ubuntu 14.10. Change-Id: I3d7202957c082974689f2a8c04d8cd33dbdc1a89 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/7722 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Dave Frodin
parent
aca2150a4f
commit
d6aa7cffa3
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@ -25,9 +25,13 @@ choice
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config BOARD_GIZMOSPHERE_GIZMO
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bool "Gizmo"
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config BOARD_GIZMOSPHERE_GIZMO2
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bool "Gizmo2"
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endchoice
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source "src/mainboard/gizmosphere/gizmo/Kconfig"
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source "src/mainboard/gizmosphere/gizmo2/Kconfig"
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config MAINBOARD_VENDOR
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string
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@ -38,7 +38,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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{AGESA_DO_RESET, agesa_Reset },
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{AGESA_READ_SPD, agesa_ReadSpd },
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{AGESA_READ_SPD, agesa_ReadSpd_from_cbfs },
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{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
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{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
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{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
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@ -50,29 +50,29 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
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/**
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* AMD Olivehill Platform ALC272 Verb Table
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* ALC272 Verb Table
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*/
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static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = {
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const CODEC_ENTRY Alc272_VerbTbl[] = {
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{0x11, 0x411111F0}, // - SPDIF_OUT2
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{0x12, 0x411111F0}, // - DMIC_1/2
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{0x13, 0x411111F0}, // - DMIC_3/4
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{0x14, 0x411111F0}, // Port D - LOUT1
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{0x15, 0x411111F0}, // Port A - LOUT2
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{0x15, 0x01011050}, // Port A - LOUT2 Explorer 2x DAC
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{0x16, 0x411111F0}, //
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{0x17, 0x411111F0}, // Port H - MONO
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{0x18, 0x01a19840}, // Port B - MIC1
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{0x18, 0x01a11840}, // Port B - MIC1
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{0x19, 0x411111F0}, // Port F - MIC2
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{0x1a, 0x01813030}, // Port C - LINE1
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{0x1b, 0x411111F0}, // Port E - LINE2
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{0x1a, 0x01811030}, // Port C - LINE1
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{0x1b, 0x01811020}, // Port E - LINE2 Explorer 2x ADC
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{0x1d, 0x40130605}, // - PCBEEP
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{0x1e, 0x01441120}, // - SPDIF_OUT1
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{0x21, 0x01214010}, // Port I - HPOUT
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{0x1e, 0x411111F0}, // - SPDIF_OUT1
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{0x21, 0x01211010}, // Port I - HPOUT
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{0xff, 0xffffffff}
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};
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static const CODEC_TBL_LIST OlivehillCodecTableList[] =
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static const CODEC_TBL_LIST CodecTableList[] =
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{
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{0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]},
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{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
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{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
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};
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@ -108,7 +108,7 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] =
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#define FREQ_14HZ 0xFE
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#define FREQ_11HZ 0xFF
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/* Olivehill Hardware Monitor Fan Control
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/* Hardware Monitor Fan Control
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* Hardware limitation:
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* HWM failed to read the input temperture vi I2C,
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* if other software switch the I2C switch by mistake or intention.
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@ -146,9 +146,9 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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/* IMC Fan Policy temperature thresholds */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 50; /*AC0 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 45; /*AC1 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 40; /*AC2 threshold in Celsius */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
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FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
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@ -160,9 +160,9 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
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/* IMC Fan Policy PWM Settings */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 100; /* AL0 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 99; /* AL1 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 98; /* AL2 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
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FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
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@ -206,7 +206,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
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/* Azalia Controller OEM Codec Table Pointer */
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]);
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FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
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/* Azalia Controller Front Panel OEM Table Pointer */
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/* Fan Control */
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@ -2,6 +2,7 @@
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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# Copyright (C) 2013-2014 Sage Electronic Engineering
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -17,7 +18,7 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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if BOARD_AMD_OLIVEHILL
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if BOARD_GIZMOSPHERE_GIZMO2
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -31,14 +32,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select GFXUMA
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select SPD_CACHE
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config MAINBOARD_DIR
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string
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default amd/olivehill
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default gizmosphere/gizmo2
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config MAINBOARD_PART_NUMBER
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string
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default "DB-FT3"
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default "Gizmo2"
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config HW_MEM_HOLE_SIZEK
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hex
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@ -56,10 +58,6 @@ config IRQ_SLOT_COUNT
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int
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default 11
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config ACPI_SSDTX_NUM
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int
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default 0
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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@ -68,4 +66,4 @@ config HUDSON_LEGACY_FREE
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bool
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default y
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endif # BOARD_AMD_OLIVEHILL
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endif # BOARD_GIZMOSPHERE_GIZMO2
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@ -2,6 +2,7 @@
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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# Copyright (C) 2014 Sage Electronic Engineering, LLC
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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@ -24,3 +25,23 @@ romstage-y += PlatformGnbPcie.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += PlatformGnbPcie.c
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## DIMM SPD for on-board memory
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SPD_BIN = $(obj)/spd.bin
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# Order of names in SPD_SOURCES is important!
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SPD_SOURCES = Micron_MT41J128M16JT
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do echo -e -n "\\x$$c"; \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := 0xab
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@ -0,0 +1,235 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2014 Sage Electronic Engineering, LLC.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Gizmo2 has 1GB using 4 Micron_MT41J128M16JT-125 chips
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# The datasheet is available at:
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# http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf
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# SPD contents for Gizmo2 2GB DDR3 (1600MHz PC3-12800) soldered down
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# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
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# bits[3:0]: 1 = 128 SPD Bytes Used
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# bits[6:4]: 1 = 256 SPD Bytes Total
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# bit7 : 0 = CRC covers bytes 0 ~ 125
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11
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# 1 SPD Revision -
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# 0x10 = Revision 1.0
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10
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# 2 Key Byte / DRAM Device Type
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# bits[7:0]: 0x0b = DDR3 SDRAM
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0B
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# 3 Key Byte / Module Type
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# bits[3:0]: 3 = SO-DIMM
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# bits[7:4]: reserved
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03
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bit7 : reserved
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03
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# 5 SDRAM Addressing
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# bits[2:0]: 1 = 10 Column Address Bits
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# bits[5:3]: 2 = 14 Row Address Bits
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# bits[7:6]: reserved
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11
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# 6 Module Nominal Voltage, VDD
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# bit0 : 0 = 1.5 V operable
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# bit1 : 0 = NOT 1.35 V operable
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# bit2 : 0 = NOT 1.25 V operable
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# bits[7:3]: reserved
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00
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# 7 Module Organization
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# bits[2:0]: 2 = 16 bits
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# bits[5:3]: 0 = 1 Rank
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# bits[7:6]: reserved
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02
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# 8 Module Memory Bus Width
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# bits[2:0]: 3 = Primary bus width is 64 bits
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# bits[4:3]: 0 = 0 bits (no bus width extension)
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# bits[7:5]: reserved
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03
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# 9 Fine Timebase (FTB) Dividend / Divisor
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# bits[3:0]: 0x02 divisor
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# bits[7:4]: 0x05 dividend
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# 5/2 = 2.5ps
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52
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# 10 Medium Timebase (MTB) Dividend
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# 11 Medium Timebase (MTB) Divisor
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# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
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01 08
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# 12 SDRAM Minimum Cycle Time (tCKmin)
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# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
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0A
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# 13 Reserved
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00
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# 14 CAS Latencies Supported, Least Significant Byte
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# 15 CAS Latencies Supported, Most Significant Byte
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# Cas Latencies of 11 - 5 are supported
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FE 00
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# 16 Minimum CAS Latency Time (tAAmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 17 Minimum Write Recovery Time (tWRmin)
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# 0x78 = tWR of 15ns - All DDR3 speed grades
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78
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# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
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# 0x3C = 7.5ns
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3C
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# 20 Minimum Row Precharge Delay Time (tRPmin)
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# 0x6E = 13.75ns - DDR3-1600K
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6E
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# 21 Upper Nibbles for tRAS and tRC
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# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
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# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
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11
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# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
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# 0x118 = 35ns - DDR3-1600 (see byte 21)
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18
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# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
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# 0x186 = 48.75ns - DDR3-1600K
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86
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# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
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# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
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# 0x500 = 160ns - for 2 Gigabit chips
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00 05
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# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
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# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
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3C
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# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
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# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
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3C
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# 28 Upper Nibble for tFAWmin
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# 29 Minimum Four Activate Window Delay Time (tFAWmin)
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# 0x0140 = 40ns - DDR3-1600, 2 KB page size
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01 40
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# 30 SDRAM Optional Feature
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# bit0 : 1= RZQ/6 supported
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# bit1 : 1 = RZQ/7 supported
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# bits[6:2]: reserved
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# bit7 : 1 = DLL Off mode supported
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83
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# 31 SDRAM Thermal and Refresh Options
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# bit0 : 1 = Temp up to 95c supported
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# bit1 : 0 = 85-95c uses 2x refresh rate
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# bit2 : 1 = Auto Self Refresh supported
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# bit3 : 0 = no on die thermal sensor
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# bits[6:4]: reserved
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# bit7 : 0 = partial self refresh supported
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05
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# 32 Module Thermal Sensor
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# 0 = Thermal sensor not incorporated onto this assembly
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00
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# 33 SDRAM Device Type
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# bits[1:0]: 0 = Signal Loading not specified
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# bits[3:2]: reserved
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# bits[6:4]: 0 = Die count not specified
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# bit7 : 0 = Standard Monolithic DRAM Device
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00
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# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
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# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
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# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
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# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
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# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
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00 00 00 00 00
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# 39 - 59 (reserved)
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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00 00 00 00 00
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# 60 Raw Card Extension, Module Nominal Height
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# bits[4:0]: 0 = <= 15mm tall
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# bits[7:5]: 0 = raw card revision 0-3
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00
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# 61 Module Maximum Thickness
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# bits[3:0]: 0 = thickness front <= 1mm
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# bits[7:4]: 0 = thinkness back <= 1mm
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00
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# 62 Reference Raw Card Used
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# bits[4:0]: 0 = Reference Raw card A used
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# bits[6:5]: 0 = revision 0
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# bit7 : 0 = Reference raw cards A through AL
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00
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# 63 Address Mapping from Edge Connector to DRAM
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# bit0 : 0 = standard mapping (not mirrored)
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# bits[7:1]: reserved
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00
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# 64 - 116 (reserved)
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00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00
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||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00
|
||||
|
||||
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
|
||||
# 0x0001 = AMD
|
||||
00 01
|
||||
|
||||
# 119 Module ID: Module Manufacturing Location - oem specified
|
||||
# 120 Module ID: Module Manufacture Year in BCD
|
||||
# 0x13 = 2013
|
||||
00 13
|
||||
|
||||
# 121 Module ID: Module Manufacture week
|
||||
# 0x12 = 12th week
|
||||
12
|
||||
|
||||
# 122 - 125: Module Serial Number
|
||||
53 41 47 45
|
||||
|
||||
# 126 - 127: Cyclical Redundancy Code
|
||||
00 00
|
||||
|
|
@ -84,19 +84,13 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
|
|||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
|
||||
},
|
||||
/* DP1 to FCH */
|
||||
{
|
||||
0,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
/* DP2 to HDMI1/DP */
|
||||
/* DP1 to high-speed edge connector */
|
||||
{
|
||||
DESCRIPTOR_TERMINATE_LIST,
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3)
|
||||
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
|
||||
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ Name(UOM9, 6)
|
|||
|
||||
/* USB Overcurrent GPEs */
|
||||
|
||||
#if 0 /* TODO: Update for Olivehill */
|
||||
#if 0 /* TODO: Update */
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
|
|
|
|||
|
|
@ -346,11 +346,11 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
|
|||
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
|
||||
//#define BLDCFG_IR_PIN_CONTROL 0x33
|
||||
|
||||
GPIO_CONTROL olivehill_gpio[] = {
|
||||
GPIO_CONTROL gizmo2_gpio[] = {
|
||||
{183, Function1, GpioIn | GpioOutEnB | PullUpB},
|
||||
{-1}
|
||||
};
|
||||
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
|
||||
//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&gizmo2_gpio[0])
|
||||
|
||||
// The following definitions specify the default values for various parameters in which there are
|
||||
// no clearly defined defaults to be used in the common file. The values below are based on product
|
||||
|
|
@ -437,17 +437,24 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
|
|||
// Byte6Seed, Byte7Seed, ByteEccSeed)
|
||||
// Speicifes the HW RXEN training seed for a channel of a socket
|
||||
//
|
||||
|
||||
#define SEED_WL 0x0E
|
||||
WRITE_LEVELING_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
|
||||
SEED_WL),
|
||||
|
||||
#define SEED_A 0x12
|
||||
HW_RXEN_SEED(
|
||||
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
|
||||
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
|
||||
SEED_A),
|
||||
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
|
||||
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
|
||||
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
|
||||
MOTHER_BOARD_LAYERS (LAYERS_4),
|
||||
MOTHER_BOARD_LAYERS (LAYERS_6),
|
||||
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
|
||||
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
|
||||
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
|
||||
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
|
||||
|
|
|
|||
|
|
@ -29,14 +29,14 @@ chip northbridge/amd/agesa/family16kb/root_complex
|
|||
|
||||
chip northbridge/amd/agesa/family16kb # PCI side of HT root complex
|
||||
device pci 0.0 on end # Root Complex
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
|
||||
device pci 1.0 on end # Internal Graphics P2P bridge 0x9835
|
||||
device pci 1.1 on end # Internal Multimedia
|
||||
device pci 2.0 on end # PCIe Host Bridge
|
||||
device pci 2.1 on end # x4 PCIe slot
|
||||
device pci 2.2 on end # mPCIe slot
|
||||
device pci 2.3 on end # Realtek NIC
|
||||
device pci 2.4 on end # Edge Connector
|
||||
device pci 2.5 on end # Edge Connector
|
||||
device pci 2.1 on end # PCIe GFX Bridge
|
||||
device pci 2.2 on end # PCIe GPP mini PCIe
|
||||
device pci 2.3 on end # PCIe LAN
|
||||
device pci 2.4 on end # PCIe x2 to high speed edge connector
|
||||
device pci 2.5 on end # PCIe x2 to high speed edge connector
|
||||
end #chip northbridge/amd/agesa/family16kb
|
||||
|
||||
chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
|
||||
|
|
@ -46,14 +46,7 @@ chip northbridge/amd/agesa/family16kb/root_complex
|
|||
device pci 12.2 on end # USB
|
||||
device pci 13.0 on end # USB
|
||||
device pci 13.2 on end # USB
|
||||
device pci 14.0 on # SM
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.0 on end # SM
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x439d
|
||||
device pci 14.7 on end # SD
|
||||
|
|
@ -65,11 +58,6 @@ chip northbridge/amd/agesa/family16kb/root_complex
|
|||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
device pci 18.5 on end
|
||||
register "spdAddrLookup" = "
|
||||
{
|
||||
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
|
||||
}"
|
||||
|
||||
end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex
|
||||
end #domain
|
||||
|
|
|
|||
Loading…
Reference in New Issue