peppy: RAM_ID + storage changes for next build.

- Update RAM_ID table.
- Add DEVSLP0 signal to NGFF SATA port.

Note: After this change, old Micron 2GB boards will no longer boot.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: Id68a1d6ace2702cca9c37305726cd55a0bde5005
Reviewed-on: https://gerrit.chromium.org/gerrit/60167
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Dave Parker <dparker@chromium.org>
Commit-Queue: Dave Parker <dparker@chromium.org>
Reviewed-on: http://review.coreboot.org/4340
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/mainboard/google/peppy/gpio.h

@@ -56,7 +56,7 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = {
 	LP_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSWARN_L */
 	LP_GPIO_NATIVE,        /* 31: NATIVE: ACPRESENT */
 	LP_GPIO_NATIVE,        /* 32: NATIVE: LPC_CLKRUN_L */
-	LP_GPIO_UNUSED,        /* 33: UNUSED */
+	LP_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
 	LP_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
 	LP_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
 	LP_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */

src/mainboard/google/peppy/romstage.c

@@ -92,10 +92,9 @@ static void copy_spd(struct pei_data *peid)
 	if (spd_file->len < sizeof(peid->spd_data[0]))
 		die("Missing SPD data.");
 
-	/* Index 0 is 2GB config with CH0 only. This is suject to change.
-	 * TODO(shawnn): Check the decoding before next build.
-	 */
-	if (spd_index == 0)
+	/* Index 0-2 are 4GB config with both CH0 and CH1
+	 * Index 4-6 are 2GB config with CH0 only */
+	if (spd_index > 3)
 		peid->dimm_channel1_disabled = 3;
 
 	memcpy(peid->spd_data[0],