src/cpu/intel: Set get_ia32_fsb function common
Add get_ia32_fsb returns FSB values in MHz of intel's CPUs. Also add get_ia32_fsb_x3 function. It returns round up 3 * get_ia32_fsb. Change-Id: I232bf88de7ebba6ac5865db046ce79e9b2f3ed28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30103 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1 +1,5 @@
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ramstage-y += common_init.c
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romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
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ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c
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postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c
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@ -0,0 +1,85 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/fsb.h>
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#include <console/console.h>
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#include <commonlib/helpers.h>
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int get_ia32_fsb(void)
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{
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struct cpuinfo_x86 c;
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static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
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static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
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static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
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msr_t msr;
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int ret = -2;
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get_fms(&c, cpuid_eax(1));
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switch (c.x86) {
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case 0x6:
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switch (c.x86_model) {
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case 0xe: /* Core Solo/Duo */
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case 0x1c: /* Atom */
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ret = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
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break;
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case 0xf: /* Core 2 or Xeon */
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case 0x17: /* Enhanced Core */
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ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
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break;
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case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
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case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
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case 0x3c: /* Haswell BCLK fixed at 100MHz */
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case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
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ret = 100;
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break;
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}
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break;
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case 0xf: /* Netburst */
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msr = rdmsr(MSR_EBC_FREQUENCY_ID);
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switch (c.x86_model) {
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case 0x2:
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ret = f2x_fsb[(msr.lo >> 16) & 7];
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break;
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case 0x3:
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case 0x4:
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case 0x6:
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ret = core2_fsb[(msr.lo >> 16) & 7];
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break;
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}
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}
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if (ret == -1)
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printk(BIOS_ERR, "FSB not found\n");
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if (ret == -2)
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printk(BIOS_ERR, "CPU not supported\n");
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return ret;
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}
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/**
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* @brief Returns three times the FSB clock in MHz
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*
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* The result of calculations with the returned value shall be divided by 3.
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* This helps to avoid rounding errors.
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*/
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int get_ia32_fsb_x3(void)
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{
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const int fsb = get_ia32_fsb();
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if (fsb > 0)
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return 100 * DIV_ROUND_CLOSEST(3 * fsb, 100);
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printk(BIOS_ERR, "FSB not supported or not found\n");
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return -1;
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}
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@ -21,6 +21,7 @@
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#include <arch/io.h>
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#include <arch/cpu.h>
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#include <arch/early_variables.h>
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#include <cpu/intel/fsb.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/intel/speedstep.h>
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@ -44,53 +45,13 @@ static u32 g_timer_fsb CAR_GLOBAL;
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static int set_timer_fsb(void)
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{
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struct cpuinfo_x86 c;
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int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
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int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
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int f2x_fsb[8] = { 100, 133, 200, 166, -1, -1, -1, -1 };
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msr_t msr;
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int ia32_fsb = get_ia32_fsb();
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get_fms(&c, cpuid_eax(1));
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switch (c.x86) {
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case 0x6:
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switch (c.x86_model) {
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case 0xe: /* Core Solo/Duo */
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case 0x1c: /* Atom */
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car_set_var(g_timer_fsb,
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core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
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return 0;
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case 0xf: /* Core 2 or Xeon */
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case 0x17: /* Enhanced Core */
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car_set_var(g_timer_fsb,
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core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]);
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return 0;
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case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
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case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
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case 0x3c: /* Haswell BCLK fixed at 100MHz */
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case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
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car_set_var(g_timer_fsb, 100);
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return 0;
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default:
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car_set_var(g_timer_fsb, 200);
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if (ia32_fsb > 0) {
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car_set_var(g_timer_fsb, ia32_fsb);
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return 0;
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}
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case 0xf: /* Netburst */
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msr = rdmsr(MSR_EBC_FREQUENCY_ID);
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switch (c.x86_model) {
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case 0x2:
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car_set_var(g_timer_fsb,
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f2x_fsb[(msr.lo >> 16) & 7]);
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return 0;
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case 0x3:
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case 0x4:
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case 0x6:
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car_set_var(g_timer_fsb,
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core2_fsb[(msr.lo >> 16) & 7]);
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return 0;
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} /* default: fallthrough */
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default:
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return -1;
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}
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}
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static inline u32 get_timer_fsb(void)
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@ -0,0 +1,30 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef CPU_INTEL_FSB_H
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#define CPU_INTEL_FSB_H
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/*
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* This function returns:
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* the system bus speed value in MHz
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* -1 if FSB is not found
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* -2 if the CPU is not supported
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*/
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int get_ia32_fsb(void);
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/*
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* This function returns round up 3 * get_ia32_fsb()
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*/
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int get_ia32_fsb_x3(void);
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#endif /* CPU_INTEL_FSB_H */
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