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amd/stoneyridge: Move SB index/data pairs to iomap.h 

Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM.

Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22723
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2017-11-29 09:46:28 -07:00 committed by Martin Roth
parent 3a7de79885
commit d77c764dd1
2 changed files with 7 additions and 8 deletions
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6
src/soc/amd/stoneyridge/include/soc/iomap.h
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@ -51,6 +51,12 @@
#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ #define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
#define SMB_BASE_ADDR 0xb00 #define SMB_BASE_ADDR 0xb00
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define AB_INDX 0xcd8 #define AB_INDX 0xcd8
#define AB_DATA (AB_INDX+4) #define AB_DATA (AB_INDX+4)
#define SYS_RESET 0xcf9 #define SYS_RESET 0xcf9

9
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -30,14 +30,7 @@
#define PSP_BAR_ENABLES 0x48 #define PSP_BAR_ENABLES 0x48
#define PSP_MAILBOX_BAR_EN 0x10 #define PSP_MAILBOX_BAR_EN 0x10
/* Power management index/data registers */ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
#define PM_PCI_CTRL 0x08 #define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_SLPSTATE_RETRY BIT(25)
#define FORCE_STPCLK_RETRY BIT(24) #define FORCE_STPCLK_RETRY BIT(24)