soc/amd/picasso: Update SMI sources
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I42bb0edb6fa2c6fa92829ef5d3623483aa448a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33771 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Marshall Dawson
Martin Roth
parent
40bc485745
commit
d881367c08
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -33,67 +33,66 @@
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# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X))
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/* SMI source and status */
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#define SMITYPE_AGPIO65 0
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#define SMITYPE_AGPIO66 1
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#define SMITYPE_AGPIO3 2
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#define SMITYPE_LPCPME_AGPIO22 3
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#define SMITYPE_GPIO4 4
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#define SMITYPE_LPCPD_AGPIOG21 5
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#define SMITYPE_IRTX1_G15 6
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#define SMITYPE_AGPIO5_DEVSLP0 7
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#define SMITYPE_WAKE_AGPIO2 8
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#define SMITYPE_APIO68_SGPIOCLK 9
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#define SMITYPE_AGPIO6 10
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#define SMITYPE_GPIO7 11
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#define SMITYPE_USBOC0_TRST_AGPIO16 12
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#define SMITYPE_USB0C1_TDI_AGPIO17 13
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#define SMITYPE_USBOC2_TCK_AGPIO18 14
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#define SMITYPE_TDO_USB0C3_AGPIO24 15
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#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16
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/* 17 Reserved */
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#define SMITYPE_BLINK_AGPIO11_USBOC7 18
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#define SMITYPE_SYSRESET_AGPIO1 19
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#define SMITYPE_IRRX1_AGPIO15 20
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#define SMITYPE_IRTX0_USBOC5_AGPIO13 21
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#define SMITYPE_GPIO9_SERPORTRX 22
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#define SMITYPE_GPIO8_SEPORTTX 23
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#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \
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| (1 << SMITYPE_AGPIO66) \
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| (1 << SMITYPE_AGPIO3) \
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| (1 << SMITYPE_LPCPME_AGPIO22) \
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| (1 << SMITYPE_GPIO4) \
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| (1 << SMITYPE_LPCPD_AGPIOG21) \
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| (1 << SMITYPE_IRTX1_G15) \
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| (1 << SMITYPE_AGPIO5_DEVSLP0) \
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| (1 << SMITYPE_WAKE_AGPIO2) \
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| (1 << SMITYPE_APIO68_SGPIOCLK) \
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| (1 << SMITYPE_AGPIO6) \
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| (1 << SMITYPE_GPIO7) \
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| (1 << SMITYPE_USBOC0_TRST_AGPIO16) \
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| (1 << SMITYPE_USB0C1_TDI_AGPIO17) \
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| (1 << SMITYPE_USBOC2_TCK_AGPIO18) \
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| (1 << SMITYPE_TDO_USB0C3_AGPIO24) \
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| (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \
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| (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \
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| (1 << SMITYPE_SYSRESET_AGPIO1) \
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| (1 << SMITYPE_IRRX1_AGPIO15) \
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| (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \
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| (1 << SMITYPE_GPIO9_SERPORTRX))
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#define SMITYPE_EHCI0_WAKE 24
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#define SMITYPE_EHCI1_WAKE 25
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#define SMITYPE_G_GENINT1_L 0
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#define SMITYPE_G_GENINT2_L 1
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#define SMITYPE_G_AGPIO3 2
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#define SMITYPE_G_LPCPME 3
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#define SMITYPE_G_AGPIO4 4
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#define SMITYPE_G_LPCPD 5
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#define SMITYPE_G_SPKR 6
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#define SMITYPE_G_AGPIO5 7
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#define SMITYPE_G_WAKE_L 8
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#define SMITYPE_G_LPC_SMI_L 9
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#define SMITYPE_G_AGPIO6 10
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#define SMITYPE_G_AGPIO7 11
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#define SMITYPE_G_USBOC0_L 12
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#define SMITYPE_G_USBOC1_L 13
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#define SMITYPE_G_USBOC2_L 14
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#define SMITYPE_G_USBOC3_L 15
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#define SMITYPE_G_AGPIO23 16
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#define SMITYPE_G_ESPI_RESET_L 17
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#define SMITYPE_G_FANIN0 18
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#define SMITYPE_G_SYSRESET_L 19
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#define SMITYPE_G_AGPIO40 20
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#define SMITYPE_G_PWR_BTN_L 21
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#define SMITYPE_G_AGPIO9 22
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#define SMITYPE_G_AGPIO8 23
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#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \
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| (1 << SMITYPE_G_GENINT2_L) \
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| (1 << SMITYPE_G_AGPIO3) \
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| (1 << SMITYPE_G_LPCPME) \
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| (1 << SMITYPE_G_AGPIO4) \
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| (1 << SMITYPE_G_LPCPD) \
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| (1 << SMITYPE_G_SPKR) \
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| (1 << SMITYPE_G_AGPIO5) \
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| (1 << SMITYPE_G_WAKE_L) \
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| (1 << SMITYPE_G_LPC_SMI_L) \
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| (1 << SMITYPE_G_AGPIO6) \
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| (1 << SMITYPE_G_AGPIO7) \
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| (1 << SMITYPE_G_USBOC0_L) \
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| (1 << SMITYPE_G_USBOC1_L) \
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| (1 << SMITYPE_G_USBOC2_L) \
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| (1 << SMITYPE_G_USBOC3_L) \
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| (1 << SMITYPE_G_AGPIO23) \
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| (1 << SMITYPE_G_ESPI_RESET_L) \
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| (1 << SMITYPE_G_FANIN0) \
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| (1 << SMITYPE_G_SYSRESET_L) \
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| (1 << SMITYPE_G_AGPIO40) \
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| (1 << SMITYPE_G_PWR_BTN_L))
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#define SMITYPE_MP2_WAKE 24
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#define SMITYPE_MP2_GPIO0 25
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#define SMITYPE_ESPI_SYS 26
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#define SMITYPE_ESPI_WAKE_PME 27
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/* 28-32 Reserved */
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#define SMITYPE_FCH_FAKE0 33
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#define SMITYPE_FCH_FAKE1 34
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#define SMITYPE_FCH_FAKE2 35
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/* 36 Reserved */
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#define SMITYPE_SATA_GEVENT0 37
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#define SMITYPE_SATA_GEVENT1 38
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#define SMITYPE_ACP_WAKE 39
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#define SMITYPE_ECG 40
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#define SMITYPE_MP2_GPIO1 28
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#define SMITYPE_GPP_PME 29
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#define SMITYPE_NB_GPP_HOT_PLUG 30
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/* 31 Reserved */
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#define SMITYPE_WAKE_L2 32
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/* 33 - 38 Reserved */
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#define SMITYPE_AZPME 39
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#define SMITYPE_USB_PD_I2C4 40
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#define SMITYPE_GPIO_CTL 41
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#define SMITYPE_CIR_PME 42
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/* 42 Reserved */
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#define SMITYPE_ALT_HPET_ALARM 43
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#define SMITYPE_FAN_THERMAL 44
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#define SMITYPE_ASF_MASTER_SLAVE 45
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@ -108,15 +107,17 @@
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#define SMITYPE_NB_SCI 54
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#define SMITYPE_RAS_SERR 55
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#define SMITYPE_XHC0_PME 56
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/* 57 Reserved */
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#define SMITYPE_XHC1_PME 57
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#define SMITYPE_ACDC_TIMER 58
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/* 59-62 Reserved */
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#define SMITYPE_TEMP_TSI 63
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/* 59-63 Reserved */
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#define SMITYPE_KB_RESET 64
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#define SMITYPE_SLP_TYP 65
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#define SMITYPE_AL2H_ACPI 66
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#define SMITYPE_AHCI 67
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/* 68-71 Reserved */
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#define SMITYPE_NB_GPP_PME_PULSE 68
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#define SMITYPE_NB_GPP_HP_PULSE 69
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#define SMITYPE_USBPD_I2C_INT 70
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/* 71 Reserved */
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#define SMITYPE_GBL_RLS 72
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#define SMITYPE_BIOS_RLS 73
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#define SMITYPE_PWRBUTTON_DOWN 74
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@ -124,32 +125,28 @@
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#define SMITYPE_USB_SMI 76
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#define SMITYPE_SERIRQ 77
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#define SMITYPE_SMBUS0_INTR 78
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#define SMITYPE_XHC_ERROR 80
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/* 79-80 Reserved */
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#define SMITYPE_INTRUDER 81
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#define SMITYPE_VBAT_LOW 82
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#define SMITYPE_PROTHOT 83
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#define SMITYPE_PCI_SERR 84
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#define SMITYPE_GPP_SERR 85
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/* 85-88 Reserved */
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#define SMITYPE_TMERTRIP 89
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/* 85-89 Reserved */
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#define SMITYPE_EMUL60_64 90
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#define SMITYPE_USB_FLR 91
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#define SMITYPE_SATA_FLR 92
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#define SMITYPE_AZ_FLR 93
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/* 94-132 Reserved */
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/* 91-132 Reserved */
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#define SMITYPE_FANIN0 133
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/* 134-137 Reserved */
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#define SMITYPE_FAKE0 138
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#define SMITYPE_FAKE1 139
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#define SMITYPE_FAKE2 140
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/* 141 Reserved */
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/* 134-140 Reserved */
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#define SMITYPE_CF9_WRITE 141
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#define SMITYPE_SHORT_TIMER 142
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#define SMITYPE_LONG_TIMER 143
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#define SMITYPE_AB_SMI 144
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#define SMITYPE_SOFT_RESET 145
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/* 146-147 Reserved */
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/* 145 Reserved */
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#define SMITYPE_ESPI_SMI 146
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/* 147 Reserved */
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#define SMITYPE_IOTRAP0 148
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/* 149-151 Reserved */
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#define SMITYPE_IOTRAP1 149
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#define SMITYPE_IOTRAP2 150
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#define SMITYPE_IOTRAP3 151
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#define SMITYPE_MEMTRAP0 152
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/* 153-155 Reserved */
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#define SMITYPE_CFGTRAP0 156
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