mainboard/amenia: add the inital files for amenia board
Add amenia board files Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/14352 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Zhao, Lijian
Martin Roth
parent
d68a13a602
commit
d8d42c2f5f
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if BOARD_INTEL_AMENIA
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_INTEL_APOLLOLAKE
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select BOARD_ROMSIZE_KB_8192
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select MAINBOARD_HAS_CHROMEOS
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_LPC_TPM
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select HAVE_ACPI_RESUME
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select MAINBOARD_HAS_CHROMEOS
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config CHROMEOS
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bool
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default y
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config MAINBOARD_DIR
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string
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default intel/amenia
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config MAINBOARD_PART_NUMBER
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string
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default "Amenia"
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config MAINBOARD_VENDOR
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string
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default "Intel"
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config FMAP_FILE
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string
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default "amenia"
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config PREBUILT_SPI_IMAGE
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string
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default "amenia.bin.orig.a0"
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config IFD_BIOS_END
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hex
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default 0x6FF000
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config IFD_BIOS_START
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hex
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default 0x1000
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config FLASHMAP_OFFSET
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 8
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endif # BOARD_INTEL_AMENIA
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@ -0,0 +1,3 @@
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config BOARD_INTEL_AMENIA
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bool "Amenia"
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@ -0,0 +1,5 @@
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += mainboard.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs.h>
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Scope (\_SB.PCI0.I2C4)
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{
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Device (ETPA)
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{
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Name (_HID, "ELAN0000")
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Name (_DDN, "Elan Touchpad")
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Name (_UID, 1)
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Name (ISTP, 1) /* Touchpad */
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Name (_CRS, ResourceTemplate()
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{
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I2cSerialBus (
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0x15, // SlaveAddress
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ControllerInitiated, // SlaveMode
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400000, // ConnectionSpeed
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AddressingMode7Bit, // AddressingMode
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"\\_SB.PCI0.I2C4", // ResourceSource
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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GPIO_18_IRQ
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}
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})
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Method (_STA)
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{
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Return (0xF)
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}
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}
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}
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@ -0,0 +1,47 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <soc/acpi.h>
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
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{
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acpi_header_t *header = &(fadt->header);
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memset(fadt, 0, sizeof(acpi_fadt_t));
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memcpy(header->signature, "FACP", 4);
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header->length = sizeof(acpi_fadt_t);
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header->revision = 5;
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memcpy(header->oem_id, OEM_ID, ARRAY_SIZE(header->oem_id));
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memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, ARRAY_SIZE(header->oem_table_id));
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memcpy(header->asl_compiler_id, ASLC, ARRAY_SIZE(header->asl_compiler_id));
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header->asl_compiler_revision = 1;
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fadt->firmware_ctrl = (uintptr_t)facs;
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fadt->dsdt = (uintptr_t)dsdt;
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fadt->model = 1;
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fadt->preferred_pm_profile = PM_MOBILE;
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fadt->x_firmware_ctl_l = (uintptr_t)facs;
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fadt->x_firmware_ctl_h = 0;
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fadt->x_dsdt_l = (uintptr_t)dsdt;
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fadt->x_dsdt_h = 0;
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soc_fill_common_fadt(fadt);
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header->checksum = acpi_checksum((void *)fadt, header->length);
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}
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@ -0,0 +1,4 @@
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Vendor name: Intel
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Board name: Amenia Board
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Category: eval
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Flashrom support: y
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@ -0,0 +1,40 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <vendorcode/google/chromeos/chromeos.h>
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int get_lid_switch(void)
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{
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/* Default to force open */
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return 1;
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}
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/* The dev-switch is virtual */
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int get_developer_mode_switch(void)
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{
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return 0;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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int get_write_protect_state(void)
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{
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return 0;
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}
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@ -0,0 +1,37 @@
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FLASH 8M {
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WP_RO 4M {
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SI_ALL 2M {
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SI_DESC 4K
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bootblock@509056 32K
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}
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RO_SECTION@2M 2M {
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FMAP 2K
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RO_FRID 0x40
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RO_VPD @4K 16K
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COREBOOT(CBFS)
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SIGN_CSE@0x180000 64K
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GBB
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}
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}
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MISC_RW {
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RW_MRC_CACHE 64K
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RW_ELOG 16K
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RW_SHARED 16K {
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SHARED_DATA 8K
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VBLOCK_DEV 8K
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}
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RW_VPD 8K
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}
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RW_SECTION_A 0xf0000 {
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VBLOCK_A 64K
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FW_MAIN_A(CBFS) 768K
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RW_FWID_A 64
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}
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RW_SECTION_B 0xf0000 {
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VBLOCK_B 64K
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FW_MAIN_B(CBFS) 768K
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RW_FWID_B 64
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}
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DEVICE_EXTENSION@7M 1M
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}
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@ -0,0 +1,31 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <boot/coreboot_tables.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, 0, "write protect"},
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{-1, ACTIVE_HIGH, 0, "recovery"},
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{-1, ACTIVE_HIGH, 1, "developer"},
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{-1, ACTIVE_HIGH, 1, "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, 0, "oprom"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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chip soc/intel/apollolake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
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register "pcie_rp2_clkreq_pin" = "0" # SSD
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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device pci 00.2 on end # - NPK
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device pci 02.0 on end # - Gen
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device pci 03.0 on end # - Iunit
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device pci 0d.0 on end # - P2SB
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device pci 0d.1 on end # - PMC
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device pci 0d.2 on end # - SPI
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device pci 0d.3 on end # - Shared SRAM
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device pci 0e.0 on end # - Audio
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device pci 11.0 on end # - ISH
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device pci 12.0 on end # - SATA
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device pci 13.0 on end # - PCIe-A 0
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device pci 13.2 on end # - Onboard Lan
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device pci 13.3 on end # - PCIe-A 3
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device pci 14.0 on end # - PCIe-B 0
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device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
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device pci 15.0 on end # - XHCI
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device pci 15.1 on end # - XDCI
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device pci 16.0 on end # - I2C 0
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device pci 16.1 on end # - I2C 1
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device pci 16.2 on end # - I2C 2
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device pci 16.3 on end # - I2C 3
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device pci 17.0 on end # - I2C 4
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device pci 17.1 on end # - I2C 5
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device pci 17.2 on end # - I2C 6
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device pci 17.3 on end # - I2C 7
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device pci 18.0 on end # - UART 0
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device pci 18.1 on end # - UART 1
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device pci 18.2 on end # - UART 2
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device pci 18.3 on end # - UART 3
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device pci 19.0 on end # - SPI 0
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device pci 19.1 on end # - SPI 1
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device pci 19.2 on end # - SPI 2
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device pci 1a.0 on end # - PWM
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device pci 1b.0 on end # - SDCARD
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device pci 1c.0 on end # - eMMC
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device pci 1e.0 on end # - SDIO
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device pci 1f.0 on end # - LPC
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device pci 1f.1 on end # - SMBUS
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end
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end
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@ -0,0 +1,39 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI v2.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/apollolake/acpi/northbridge.asl>
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#include <soc/intel/apollolake/acpi/southbridge.asl>
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}
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}
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/* Mainboard Specific devices */
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#include "acpi/mainboard.asl"
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/* Chipset specific sleep states */
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#include <soc/intel/apollolake/acpi/sleepstates.asl>
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <device/device.h>
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#include <soc/gpio.h>
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/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */
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static const struct pad_config amenia_gpios[] = {
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PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/
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PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/
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PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */
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PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */
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PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */
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PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */
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PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), /* SOC_WAKE_SCI_N */
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PAD_CFG_GPI_APIC(GPIO_18, UP_20K, DEEP, LEVEL, NONE), /* Trackpad_INT_N */
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PAD_CFG_GPI_APIC(GPIO_19, UP_20K, DEEP, LEVEL, NONE), /* Audio_Jack_Present_N */
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PAD_CFG_GPI_APIC(GPIO_21, UP_20K, DEEP, LEVEL, NONE), /* TCH_INT_N */
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PAD_CFG_GPI_APIC(GPIO_22, UP_20K, DEEP, LEVEL, NONE), /* EC_SOC_WAKE_1P8_N */
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PAD_CFG_GPO(GPIO_23, 1, DEEP), /* GPS_NSTANDBY */
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PAD_CFG_GPO(GPIO_24, 1, DEEP), /* SSD_SATA_DEVSLP */
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PAD_CFG_GPI_APIC(GPIO_30, UP_20K, DEEP, LEVEL, NONE), /* EC_KBD_IRQ_SOC_N */
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PAD_CFG_NF(GPIO_32, NATIVE, DEEP, NF5), /* GPS_SUSCLK_32K */
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PAD_CFG_GPI(GPIO_33, UP_20K, DEEP), /* EC_KBD_IRQ_SOC_N */
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PAD_CFG_GPO(GPIO_36, 0, DEEP), /* TOUCH_PNL_RST */
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PAD_CFG_NF(GPIO_37, NATIVE, DEEP, NF1), /* SOC_BUZZER */
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PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS_B */
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PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* GPS_UART_RXD */
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PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* GPS_UART_TXD */
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PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* GPS_UART_RTS_B */
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PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* GPS_UART_CTS_N */
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PAD_CFG_GPI_SMI(GPIO_49, UP_20K, DEEP, LEVEL, NONE), /* EC_SMI_N */
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PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* SPI_WP_STAT */
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PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* DMIC_CLK_A1 */
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PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* DMIC_CLK_B1 */
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PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* DMIC_DATA_1 */
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PAD_CFG_NF(GPIO_82, NATIVE, DEEP, NF1), /* DMIC_CLK_AB2 */
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PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* DMIC_DATA_2 */
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PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* MCLK */
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PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* I2S2_BCLK_AMP */
|
||||
PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* I2S2_SYNC_AMP */
|
||||
PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* I2S2_SDI_AMP */
|
||||
PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* I2S2_SDO_AMP */
|
||||
PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
|
||||
PAD_CFG_GPI_APIC(GPIO_116, UP_20K, DEEP, LEVEL, INVERT), /* AUDIO_CODEC_IRQ_N */
|
||||
|
||||
PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* I2C_SDA for Audio Codec */
|
||||
PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* I2C_SCL for Audio Codec */
|
||||
|
||||
PAD_CFG_NF(GPIO_128, UP_5K, DEEP, NF1), /* I2C_SDA for ALS */
|
||||
PAD_CFG_NF(GPIO_129, UP_5K, DEEP, NF1), /* I2C_SCL for ALS */
|
||||
|
||||
PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* I2C_SDA for Touch Screen */
|
||||
PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* I2C_SCL for Touchscreen */
|
||||
|
||||
PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* I2C_SDA for Trackpad */
|
||||
PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* I2C_SCL for Trackpad */
|
||||
|
||||
PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* I2S6_BCLK_Codec */
|
||||
PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* I2S6_SYNC_Codec */
|
||||
PAD_CFG_NF(GPIO_148, NATIVE, DEEP, NF2), /* I2S6_SDI_Codec */
|
||||
PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* I2S6_SDO_Codec */
|
||||
|
||||
PAD_CFG_GPO(GPIO_150, 1, DEEP), /* WIFI_PERST_1P8_N */
|
||||
PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* RSVD (ISH_BASE_ACCEL_INT_N) */
|
||||
PAD_CFG_GPI(GPIO_152, UP_20K, DEEP), /* RSVD (ALS_IRQ_N) */
|
||||
|
||||
PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */
|
||||
PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */
|
||||
|
||||
|
||||
PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */
|
||||
PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */
|
||||
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
|
||||
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
|
||||
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
|
||||
PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_B */
|
||||
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
|
||||
PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */
|
||||
PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */
|
||||
|
||||
|
||||
/* Configure eMMC pins for proper pull UP/DN */
|
||||
PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */
|
||||
PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */
|
||||
PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC0_D1 */
|
||||
PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC0_D2 */
|
||||
PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC0_D3 */
|
||||
PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC0_D4 */
|
||||
PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC0_D5 */
|
||||
PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC0_D6 */
|
||||
PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC0_D7 */
|
||||
PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */
|
||||
PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */
|
||||
|
||||
PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */
|
||||
PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */
|
||||
|
||||
PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */
|
||||
PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */
|
||||
|
||||
PAD_CFG_NF(GPIO_205, NATIVE, DEEP, NF1), /* PCIE_WLAN_WAKE3_N */
|
||||
PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_SSD_WAKE0_N */
|
||||
PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), /* SSD CLKREQ */
|
||||
PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), /* Wifi CLKREQ */
|
||||
|
||||
PAD_CFG_GPO(PMU_BATLOW_B, 0, DEEP), /* EMMC_PLTRST_N ?? */
|
||||
PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */
|
||||
PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */
|
||||
|
||||
PAD_CFG_NF(GPIO_199,NATIVE,DEEP,NF2), /* HV_DDI1_HPD */
|
||||
PAD_CFG_NF(GPIO_200,NATIVE,DEEP,NF2), /* HV_DDI0_HPD */
|
||||
PAD_CFG_NF(PMC_SPI_FS1,NATIVE,DEEP,NF2), /* HV_DDI2_HPD */
|
||||
|
||||
};
|
||||
|
||||
static void mainboard_init(void *chip_info)
|
||||
{
|
||||
gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios));
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.init = mainboard_init,
|
||||
};
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corp.
|
||||
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
#include <soc/fsp/FspmUpd.h>
|
||||
|
||||
/* Channel 0 PHY to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch0_amenia[] = {
|
||||
9, 14, 12, 13, 10, 11, 8, 15, 7, 3, 5, 2, 6, 0, 1, 4,
|
||||
28, 24, 26, 27, 29, 30, 31, 25, 20, 22, 23, 16, 19, 17, 18, 21,
|
||||
};
|
||||
|
||||
/* Channel 1 PHY to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch1_amenia[] = {
|
||||
6, 7, 5, 4, 3, 1, 0, 2, 12, 10, 11, 13, 14, 8, 9, 15,
|
||||
16, 22, 23, 20, 18, 17, 19, 21, 30, 28, 29, 25, 24, 26, 27, 31,
|
||||
};
|
||||
|
||||
/* Channel 2 PHY to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch2_amenia[] = {
|
||||
15, 9, 8, 11, 14, 13, 12, 10, 4, 3, 7, 5, 6, 1, 0, 2,
|
||||
25, 28, 30, 31, 26, 27, 24, 29, 20, 23, 22, 21, 18, 19, 16, 17,
|
||||
};
|
||||
|
||||
/* Channel 3 PHY to DUnit DQ mapping */
|
||||
static const uint8_t swizzling_ch3_amenia[] = {
|
||||
2, 1, 6, 7, 5, 4, 3, 0, 11, 10, 8, 9, 12, 15, 13, 14,
|
||||
17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30,
|
||||
};
|
||||
|
||||
static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg)
|
||||
{
|
||||
cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */
|
||||
cfg->DIMM0SPDAddress = 0;
|
||||
cfg->DIMM1SPDAddress = 0;
|
||||
cfg->Ch0_RankEnable = 0x1;
|
||||
cfg->Ch0_DeviceWidth = 0x1;
|
||||
cfg->Ch0_DramDensity = 0x2;
|
||||
cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch0_TristateClk1 = 0;
|
||||
cfg->Ch0_Mode2N = 0;
|
||||
cfg->Ch0_OdtLevels = 0;
|
||||
cfg->Ch1_RankEnable = 0x1;
|
||||
cfg->Ch1_DeviceWidth = 0x1;
|
||||
cfg->Ch1_DramDensity = 0x2;
|
||||
cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch1_TristateClk1 = 0;
|
||||
cfg->Ch1_Mode2N = 0;
|
||||
cfg->Ch1_OdtLevels = 0;
|
||||
cfg->Ch2_RankEnable = 0x1;
|
||||
cfg->Ch2_DeviceWidth = 0x1;
|
||||
cfg->Ch2_DramDensity = 0x2;
|
||||
cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch2_TristateClk1 = 0;
|
||||
cfg->Ch2_Mode2N = 0;
|
||||
cfg->Ch2_OdtLevels = 0;
|
||||
cfg->Ch3_RankEnable = 0x1;
|
||||
cfg->Ch3_DeviceWidth = 0x1;
|
||||
cfg->Ch3_DramDensity = 0x2;
|
||||
cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */
|
||||
cfg->Ch3_TristateClk1 = 0;
|
||||
cfg->Ch3_Mode2N = 0;
|
||||
cfg->Ch3_OdtLevels = 0;
|
||||
|
||||
memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_amenia,
|
||||
sizeof(swizzling_ch0_amenia));
|
||||
memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_amenia,
|
||||
sizeof(swizzling_ch1_amenia));
|
||||
memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_amenia,
|
||||
sizeof(swizzling_ch2_amenia));
|
||||
memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_amenia,
|
||||
sizeof(swizzling_ch3_amenia));
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
|
||||
{
|
||||
struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
|
||||
|
||||
cfg->Package = 1; /* 0x1:BGA */
|
||||
cfg->MemoryDown = 1;
|
||||
cfg->DDR3LPageSize = 0;
|
||||
cfg->DDR3LASR = 0;
|
||||
cfg->ScramblerSupport = 1;
|
||||
cfg->ChannelHashMask = 0x36;
|
||||
cfg->SliceHashMask = 0x9;
|
||||
cfg->InterleavedMode = 2;
|
||||
cfg->ChannelsSlicesEnable = 0;
|
||||
cfg->MinRefRate2xEnable = 0;
|
||||
cfg->DualRankSupportEnable = 1;
|
||||
cfg->DisableFastBoot = 0;
|
||||
cfg->RmtMode = 0;
|
||||
cfg->RmtCheckRun = 0;
|
||||
cfg->RmtMarginCheckScaleHighThreshold = 0;
|
||||
cfg->MemorySizeLimit = 0x1800; /* Limit to 6GB */
|
||||
cfg->LowMemoryMaxValue = 0;
|
||||
cfg->HighMemoryMaxValue = 0;
|
||||
|
||||
amenia_fill_memory_params(cfg);
|
||||
}
|
||||
|
|
@ -38,6 +38,12 @@ config CPU_SPECIFIC_OPTIONS
|
|||
select TSC_MONOTONIC_TIMER
|
||||
select HAVE_MONOTONIC_TIMER
|
||||
select PLATFORM_USES_FSP2_0
|
||||
select HAVE_HARD_RESET
|
||||
select SOC_INTEL_COMMON
|
||||
|
||||
config SOC_INTEL_COMMON_RESET
|
||||
bool
|
||||
default y
|
||||
|
||||
config MMCONF_BASE_ADDRESS
|
||||
hex "PCI MMIO Base Address"
|
||||
|
|
|
|||
Loading…
Reference in New Issue