mb/sapphire/pureplatinumh61: Make devicetree prettier
Align contents, and fix some redundant comments. Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -30,7 +30,7 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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device domain 0x0 on
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "c2_latency" = "0x0065"
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register "gen1_dec" = "0x000c0291"
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register "gen1_dec" = "0x000c0291"
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register "gen2_dec" = "0x000c0a01"
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register "gen2_dec" = "0x000c0a01"
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@ -46,48 +46,38 @@ chip northbridge/intel/sandybridge
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{0x9f, READ_NO_ADDR},
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{0x9f, READ_NO_ADDR},
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{0xad, WRITE_NO_ADDR},
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{0xad, WRITE_NO_ADDR},
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{0x04, WRITE_NO_ADDR}}"
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{0x04, WRITE_NO_ADDR}}"
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device pci 16.0 on # Management Engine Interface 1
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 16.1 off # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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end
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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end
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device pci 19.0 off end # Intel Gigabit Ethernet
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device pci 16.3 off # Management Engine KT
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device pci 1a.0 on # USB2 EHCI #2
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end
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device pci 19.0 off # Intel Gigabit Ethernet
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end
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device pci 1a.0 on # USB2 EHCI #2
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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device pci 1b.0 on # HD Audio Controller
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subsystemid 0x8086 0x1c20
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subsystemid 0x8086 0x1c20
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end
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end
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device pci 1c.0 on # PCIe Port #1
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1c.1 off # PCIe Port #2
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device pci 1c.1 off end # PCIe Port #2
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end
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.2 off # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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end
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device pci 1c.4 on # PCIe Port #5
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device pci 1c.3 off # PCIe Port #4
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end
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device pci 1c.4 on # PCIe Port #5
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1c.5 on # PCIe Port #6
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device pci 1c.5 on # PCIe Port #6
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1c.6 off # PCIe Port #7
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device pci 1c.6 off end # PCIe Port #7
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end
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device pci 1c.7 off end # PCIe Port #8
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device pci 1c.7 off # PCIe Port #8
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device pci 1d.0 on # USB2 EHCI #1
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end
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device pci 1d.0 on # USB2 EHCI #1
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1e.0 off # PCI bridge
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device pci 1e.0 off end # PCI bridge
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end
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device pci 1f.0 on # LPC bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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chip superio/fintek/f71808a
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chip superio/fintek/f71808a
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register "multi_function_register_0" = "0x00"
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register "multi_function_register_0" = "0x00"
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@ -130,24 +120,22 @@ chip northbridge/intel/sandybridge
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end
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end
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end
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end
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end
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end
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device pci 1f.2 on # SATA Controller 1
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device pci 1f.2 on # SATA Controller 1
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1f.3 on # SMBus
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device pci 1f.3 on # SMBus
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 1f.5 off # SATA Controller 2
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device pci 1f.5 off end # SATA Controller 2
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end
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device pci 1f.6 off end # Thermal
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device pci 1f.6 off # Thermal
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end
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end
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end
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device pci 00.0 on # Host bridge Host bridge
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device pci 00.0 on # Host bridge
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 01.0 on # PCIe Bridge for discrete graphics
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device pci 01.0 on # PCIe Bridge for discrete graphics
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subsystemid 0x174b 0x1007
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subsystemid 0x174b 0x1007
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end
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end
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device pci 02.0 on # Internal graphics VGA controller
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device pci 02.0 on # Internal graphics VGA controller
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subsystemid 0x8086 0x2010
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subsystemid 0x8086 0x2010
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end
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end
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end
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end
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