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mb/sapphire/pureplatinumh61: Make devicetree prettier 

Align contents, and fix some redundant comments.

Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-01-01 18:46:34 +01:00 committed by Nico Huber
parent d1b80f0fc2
commit d913036e18
1 changed files with 26 additions and 38 deletions
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42
src/mainboard/sapphire/pureplatinumh61/devicetree.cb
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@ -49,45 +49,35 @@ chip northbridge/intel/sandybridge
device pci 16.0 on # Management Engine Interface 1
subsystemid 0x174b 0x1007
end
device pci 16.1 off # Management Engine Interface 2
end
device pci 16.2 off # Management Engine IDE-R
end
device pci 16.3 off # Management Engine KT
end
device pci 19.0 off # Intel Gigabit Ethernet
end
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on # USB2 EHCI #2
subsystemid 0x174b 0x1007
end
device pci 1b.0 on # High Definition Audio Audio controller
device pci 1b.0 on # HD Audio Controller
subsystemid 0x8086 0x1c20
end
device pci 1c.0 on # PCIe Port #1
subsystemid 0x174b 0x1007
end
device pci 1c.1 off # PCIe Port #2
end
device pci 1c.2 off # PCIe Port #3
end
device pci 1c.3 off # PCIe Port #4
end
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 on # PCIe Port #5
subsystemid 0x174b 0x1007
end
device pci 1c.5 on # PCIe Port #6
subsystemid 0x174b 0x1007
end
device pci 1c.6 off # PCIe Port #7
end
device pci 1c.7 off # PCIe Port #8
end
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on # USB2 EHCI #1
subsystemid 0x174b 0x1007
end
device pci 1e.0 off # PCI bridge
end
device pci 1f.0 on # LPC bridge PCI-LPC bridge
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
subsystemid 0x174b 0x1007
chip superio/fintek/f71808a
register "multi_function_register_0" = "0x00"
@ -136,12 +126,10 @@ chip northbridge/intel/sandybridge
device pci 1f.3 on # SMBus
subsystemid 0x174b 0x1007
end
device pci 1f.5 off # SATA Controller 2
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal
end
device pci 1f.6 off # Thermal
end
end
device pci 00.0 on # Host bridge Host bridge
device pci 00.0 on # Host bridge
subsystemid 0x174b 0x1007
end
device pci 01.0 on # PCIe Bridge for discrete graphics