mb/asrock/h110m: rewrite gpio config using macros
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 [1]
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The pad configuration in this patch was
generated using the pch-pads-parser utility [2]. The inteltool dump
before and after the patch is identical (see notes)
Notes:
1. For some reason, GPIO RX State (RO) for the GPP_F4 and GPP_G10
changed the value to 0, but this doesn't affect the motherboard
operation. Perhaps this is because PAD_CFG1_GPIO_DRIVER is set to
PAD_CFG_GPI_INT(), and the pad is not actually connected. So far I
haven't circuit diagram to check this out.
2. According to the documentation [1], the value 3h for RXEVCFG is
implemented as setting 0h.
3. If the available macros from gpio_defs.h [3] can't determine the
configuration of the pad, the utility [2] generates common
_PAD_CFG_STRUCT() macros
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
[2] https://github.com/maxpoliak/pch-pads-parser/tree/stable_1.0
[3] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Maxim Polyakov
Felix Held
parent
08aa502d79
commit
d947c691bc
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@ -13,260 +13,496 @@
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* GNU General Public License for more details.
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*/
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#ifndef _GPIO_DVS_H
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#define _GPIO_DVS_H
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#ifndef _PCH_GPIO_H
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#define _PCH_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
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_PAD_CFG_STRUCT(val, config0, config1)
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/* Pad configuration in ramstage. */
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* GPIO Group GPP_A */
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H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
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H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
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H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
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H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
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H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
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H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
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H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
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H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
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H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
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H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
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H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */
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H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
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H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
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H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
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/* GPIO Group GPP_B */
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H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */
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H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */
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H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */
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H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */
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H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */
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/* GPIO Group GPP_C */
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H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */
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H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */
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H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */
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H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */
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H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
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/* ------- GPIO Group GPP_A ------- */
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/* GPP_A0 - RCIN# */
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PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF),
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/* GPP_A1 - LAD0 */
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PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
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/* GPP_A2 - LAD1 */
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PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
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/* GPP_A3 - LAD2 */
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PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
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/* GPP_A4 - LAD3 */
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PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
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/* GPP_A5 - LFRAME# */
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PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF),
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/* GPP_A6 - SERIRQ */
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PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF),
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/* GPP_A7 - GPIO */
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PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF),
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/* GPP_A8 - CLKRUN# */
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PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF),
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/* GPP_A9 - CLKOUT_LPC0 */
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PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF),
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/* GPP_A10 - CLKOUT_LPC1 */
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PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF),
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/* GPP_A11 - GPIO */
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PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF),
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/* GPP_A12 - GPIO */
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PAD_CFG_GPI_INT(GPP_A12, NONE, PLTRST, OFF),
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/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
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PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF),
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/* GPP_A14 - SUS_STAT# */
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PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF),
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/* GPP_A15 - SUS_ACK# */
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PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF),
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/* GPP_A16 - GPIO */
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PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF),
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/* GPP_A17 - GPIO */
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PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF),
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/* GPP_A18 - GPIO */
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PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF),
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/* GPP_A19 - GPIO */
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PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF),
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/* GPP_A20 - GPIO */
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PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, OFF),
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/* GPP_A21 - GPIO */
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PAD_CFG_GPI_INT(GPP_A21, NONE, PLTRST, OFF),
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/* GPP_A22 - GPIO */
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PAD_CFG_GPI_INT(GPP_A22, NONE, PLTRST, OFF),
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/* GPP_A23 - GPIO */
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PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF),
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/* ------- GPIO Group GPP_B ------- */
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/* GPP_B0 - GPIO */
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PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF),
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/* GPP_B1 - GPIO */
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PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF),
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/* GPP_B2 - GPIO */
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PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF),
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/* GPP_B3 - GPIO */
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PAD_CFG_GPO(GPP_B3, 1, DEEP),
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/* GPP_B4 - CPU_GP3 */
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PAD_CFG_NF_BUF_TRIG(GPP_B4, NONE, PLTRST, NF1, TX_DISABLE, OFF),
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/* GPP_B5 - GPIO */
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PAD_CFG_GPI_INT(GPP_B5, NONE, PLTRST, OFF),
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/* GPP_B6 - GPIO */
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PAD_CFG_GPI_INT(GPP_B6, NONE, PLTRST, OFF),
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/* GPP_B7 - NC */
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PAD_NC(GPP_B7, NONE),
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/* GPP_B8 - GPIO */
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PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF),
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/* GPP_B9 - GPIO */
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PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF),
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/* GPP_B10 - GPIO */
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PAD_CFG_GPI_INT(GPP_B10, NONE, PLTRST, OFF),
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/* GPP_B11 - GPIO */
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_PAD_CFG_STRUCT(GPP_B11,
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PAD_FUNC(GPIO) | PAD_RESET(PWROK) |
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PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE |
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PAD_BUF(NO_DISABLE),
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PAD_PULL(NONE)),
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/* GPP_B12 - SLP_S0# */
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PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, RX_DISABLE, OFF),
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/* GPP_B13 - PLTRST# */
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PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, RX_DISABLE, OFF),
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/* GPP_B14 - SPKR */
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PAD_CFG_NF_BUF_TRIG(GPP_B14, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF),
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/* GPP_B15 - GPIO */
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PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF),
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/* GPP_B16 - GPIO */
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PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF),
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/* GPP_B17 - GPIO */
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PAD_CFG_GPO(GPP_B17, 1, DEEP),
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/* GPP_B18 - GPIO */
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PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF),
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/* GPP_B19 - GPIO */
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PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF),
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/* GPP_B20 - GPIO */
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PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF),
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/* GPP_B21 - GPIO */
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PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF),
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/* GPP_B22 - GPIO */
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PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF),
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/* GPP_B23 - PCHHOT# */
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_PAD_CFG_STRUCT(GPP_B23,
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PAD_FUNC(NF2) | PAD_RESET(PLTRST) |
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PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE |
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PAD_BUF(RX_DISABLE) | 1,
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PAD_PULL(20K_PD)),
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/* ------- GPIO Group GPP_C ------- */
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/* GPP_C0 - SMBCLK */
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PAD_CFG_NF_BUF_TRIG(GPP_C0, NONE, DEEP, NF1, TX_DISABLE, OFF),
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/* GPP_C1 - SMBDATA */
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PAD_CFG_NF_BUF_TRIG(GPP_C1, NONE, DEEP, NF1, TX_DISABLE, OFF),
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/* GPP_C2 - GPIO */
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PAD_CFG_GPO(GPP_C2, 1, DEEP),
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/* GPP_C3 - SML0CLK */
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PAD_CFG_NF_BUF_TRIG(GPP_C3, NONE, DEEP, NF1, TX_DISABLE, OFF),
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/* GPP_C4 - SML0DATA */
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PAD_CFG_NF_BUF_TRIG(GPP_C4, NONE, DEEP, NF1, TX_DISABLE, OFF),
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/* GPP_C5 - GPIO */
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PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF),
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/* GPP_C6 - RESERVED */
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/* GPP_C7 - RESERVED */
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H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */
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H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */
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H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */
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H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */
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H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */
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H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */
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H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */
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H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
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/* GPIO Group GPP_D */
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H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */
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H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */
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H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */
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H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */
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H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
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H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
|
||||
/* GPIO Group GPP_E */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */
|
||||
/* SATA_DEVSLP0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c),
|
||||
/* SATA_DEVSLP1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d),
|
||||
/* SATA_DEVSLP2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e),
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */
|
||||
/* GPIO Group GPP_F */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
|
||||
/* GPIO Group GPP_G */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
|
||||
/* GPIO Group GPP_H */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
|
||||
/* GPIO Group GPD */
|
||||
H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
|
||||
/* GPIO Group GPP_I */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
|
||||
/* DDPB_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072),
|
||||
/* DDPB_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073),
|
||||
/* DDPC_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074),
|
||||
/* DDPC_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075),
|
||||
/* DDPD_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076),
|
||||
/* DDPD_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077),
|
||||
/* GPP_C8 - UART0_RXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C8, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_C9 - UART0_TXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C9, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_C10 - UART0_RTS# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C10, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_C11 - UART0_CTS# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C11, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_C12 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C12, NONE, PLTRST, OFF),
|
||||
/* GPP_C13 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C13, NONE, PLTRST, OFF),
|
||||
/* GPP_C14 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C14, NONE, PLTRST, OFF),
|
||||
/* GPP_C15 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C15, NONE, PLTRST, OFF),
|
||||
/* GPP_C16 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF),
|
||||
/* GPP_C17 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF),
|
||||
/* GPP_C18 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF),
|
||||
/* GPP_C19 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF),
|
||||
/* GPP_C20 - UART2_RXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C20, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_C21 - UART2_TXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C21, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_C22 - UART2_RTS# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_C22, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_C23 - GPIO */
|
||||
PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES),
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
/* GPP_D0 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, OFF),
|
||||
/* GPP_D1 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, OFF),
|
||||
/* GPP_D2 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D2, NONE, PLTRST, OFF),
|
||||
/* GPP_D3 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D3, NONE, PLTRST, OFF),
|
||||
/* GPP_D4 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF),
|
||||
/* GPP_D5 - I2S_SFRM */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D5, NONE, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_D6 - I2S_TXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D6, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_D7 - I2S_RXD */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D7, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_D8 - I2S_SCLK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D8, NONE, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_D9 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, OFF),
|
||||
/* GPP_D10 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D10, NONE, PLTRST, OFF),
|
||||
/* GPP_D11 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D11, NONE, PLTRST, OFF),
|
||||
/* GPP_D12 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D12, NONE, PLTRST, OFF),
|
||||
/* GPP_D13 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF),
|
||||
/* GPP_D14 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF),
|
||||
/* GPP_D15 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF),
|
||||
/* GPP_D16 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF),
|
||||
/* GPP_D17 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, OFF),
|
||||
/* GPP_D18 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF),
|
||||
/* GPP_D19 - DMIC_CLK0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D19, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_D20 - DMIC_DATA0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_D20, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_D21 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF),
|
||||
/* GPP_D22 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D22, NONE, PLTRST, OFF),
|
||||
/* GPP_D23 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF),
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
/* GPP_E0 - SATAXPCIE0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E0, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E1 - SATAXPCIE1 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E2 - SATAXPCIE2 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E2, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E3 - CPU_GP0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E3, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E4 - SATA_DEVSLP0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E4, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E5 - SATA_DEVSLP1 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E5, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E6 - SATA_DEVSLP2 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E6, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E7 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, OFF),
|
||||
/* GPP_E8 - SATA_LED# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_E9 - USB_OC0# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E10 - USB_OC1# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E11 - USB_OC2# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_E12 - USB_OC3# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
/* GPP_F0 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF),
|
||||
/* GPP_F1 - SATAXPCIE4 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_F1, 20K_PU, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_F2 - GPIO */
|
||||
PAD_NC(GPP_F2, NONE),
|
||||
/* GPP_F3 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F3, NONE, PLTRST, OFF),
|
||||
/* GPP_F4 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F4, NONE, PLTRST, OFF),
|
||||
/* GPP_F5 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F5, NONE, PLTRST, OFF),
|
||||
/* GPP_F6 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F6, NONE, PLTRST, OFF),
|
||||
/* GPP_F7 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF),
|
||||
/* GPP_F8 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF),
|
||||
/* GPP_F9 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF),
|
||||
/* GPP_F10 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
|
||||
/* GPP_F11 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF),
|
||||
/* GPP_F12 - GPIO */
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST),
|
||||
/* GPP_F13 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST),
|
||||
/* GPP_F14 - GPIO */
|
||||
PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP),
|
||||
/* GPP_F15 - USB_OC4# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_F16 - USB_OC5# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_F17 - USB_OC6# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_F17, NONE, DEEP, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_F18 - GPIO */
|
||||
PAD_CFG_GPO(GPP_F18, 1, PLTRST),
|
||||
/* GPP_F19 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, OFF),
|
||||
/* GPP_F20 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F20, NONE, PLTRST, OFF),
|
||||
/* GPP_F21 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F21, NONE, PLTRST, OFF),
|
||||
/* GPP_F22 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F22, NONE, PLTRST, OFF),
|
||||
/* GPP_F23 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_F23, NONE, PLTRST, OFF),
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
/* GPP_G0 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G0, NONE, PWROK, OFF),
|
||||
/* GPP_G1 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G1, NONE, PWROK, OFF),
|
||||
/* GPP_G2 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G2, NONE, PWROK, OFF),
|
||||
/* GPP_G3 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G3, NONE, PWROK, OFF),
|
||||
/* GPP_G4 - GPIO */
|
||||
PAD_CFG_GPO(GPP_G4, 0, DEEP),
|
||||
/* GPP_G5 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G5, NONE, PWROK, OFF),
|
||||
/* GPP_G6 - GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_G6,
|
||||
PAD_FUNC(GPIO) | PAD_RESET(PWROK) |
|
||||
PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES |
|
||||
PAD_BUF(TX_DISABLE),
|
||||
PAD_PULL(NONE)),
|
||||
/* GPP_G7 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G7, NONE, PWROK, OFF),
|
||||
/* GPP_G8 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF),
|
||||
/* GPP_G9 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF),
|
||||
/* GPP_G10 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF),
|
||||
/* GPP_G11 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF),
|
||||
/* GPP_G12 - GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_G12,
|
||||
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) |
|
||||
PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES |
|
||||
PAD_BUF(TX_DISABLE),
|
||||
PAD_PULL(NONE)),
|
||||
/* GPP_G13 - GPIO */
|
||||
PAD_CFG_GPO(GPP_G13, 1, PLTRST),
|
||||
/* GPP_G14 - GPIO */
|
||||
_PAD_CFG_STRUCT(GPP_G14,
|
||||
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) |
|
||||
PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES |
|
||||
PAD_BUF(TX_DISABLE),
|
||||
PAD_PULL(NONE)),
|
||||
/* GPP_G15 - GPIO */
|
||||
PAD_CFG_GPO(GPP_G15, 0, PLTRST),
|
||||
/* GPP_G16 - GPIO */
|
||||
PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST),
|
||||
/* GPP_G17 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF),
|
||||
/* GPP_G18 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST),
|
||||
/* GPP_G19 - SMI# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_G20 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G20, NONE, PLTRST, OFF),
|
||||
/* GPP_G21 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G21, NONE, PLTRST, OFF),
|
||||
/* GPP_G22 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G22, NONE, PLTRST, OFF),
|
||||
/* GPP_G23 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_G23, NONE, PLTRST, OFF),
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
/* GPP_H0 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, OFF),
|
||||
/* GPP_H1 - GPIO */
|
||||
PAD_NC(GPP_H1, NONE),
|
||||
/* GPP_H2 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H2, NONE, PLTRST, OFF),
|
||||
/* GPP_H3 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H3, NONE, PLTRST, OFF),
|
||||
/* GPP_H4 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF),
|
||||
/* GPP_H5 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H5, NONE, PLTRST, OFF),
|
||||
/* GPP_H6 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H6, NONE, PLTRST, OFF),
|
||||
/* GPP_H7 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H7, NONE, PLTRST, OFF),
|
||||
/* GPP_H8 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H8, NONE, PLTRST, OFF),
|
||||
/* GPP_H9 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H9, NONE, PLTRST, OFF),
|
||||
/* GPP_H10 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF),
|
||||
/* GPP_H11 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF),
|
||||
/* GPP_H12 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF),
|
||||
/* GPP_H13 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST),
|
||||
/* GPP_H14 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST),
|
||||
/* GPP_H15 - GPIO */
|
||||
PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST),
|
||||
/* GPP_H16 - GPIO */
|
||||
PAD_CFG_GPI(GPP_H16, NONE, PLTRST),
|
||||
/* GPP_H17 - GPIO */
|
||||
PAD_CFG_GPO(GPP_H17, 1, PLTRST),
|
||||
/* GPP_H18 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF),
|
||||
/* GPP_H19 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF),
|
||||
/* GPP_H20 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF),
|
||||
/* GPP_H21 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF),
|
||||
/* GPP_H22 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF),
|
||||
/* GPP_H23 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_H23, NONE, PWROK, OFF),
|
||||
|
||||
/* -------- GPIO Group GPD -------- */
|
||||
/* GPD0 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF),
|
||||
/* GPD1 - GPIO */
|
||||
PAD_CFG_GPO(GPD1, 0, PWROK),
|
||||
/* GPD2 - LAN_WAKE# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD2, NATIVE, PWROK, NF1, RX_DISABLE, LEVEL),
|
||||
/* GPD3 - PWRBTN# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD3, 20K_PU, PWROK, NF1, TX_DISABLE, OFF),
|
||||
/* GPD4 - SLP_S3# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, RX_DISABLE, OFF),
|
||||
/* GPD5 - SLP_S4# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, RX_DISABLE, OFF),
|
||||
/* GPD6 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPD6, NONE, PLTRST, OFF),
|
||||
/* GPD7 - GPIO */
|
||||
_PAD_CFG_STRUCT(GPD7,
|
||||
PAD_FUNC(GPIO) | PAD_RESET(PLTRST) |
|
||||
PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE |
|
||||
PAD_BUF(TX_DISABLE) | 1,
|
||||
PAD_PULL(NONE)),
|
||||
/* GPD8 - SUSCLK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, RX_DISABLE, OFF),
|
||||
/* GPD9 - SLP_WLAN# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD9, NONE, PWROK, NF1, RX_DISABLE, OFF),
|
||||
/* GPD10 - SLP_S5# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPD10, NONE, PWROK, NF1, RX_DISABLE, OFF),
|
||||
/* GPD11 - GPIO */
|
||||
PAD_CFG_GPO(GPD11, 0, PWROK),
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
/* GPP_I0 - DDPB_HPD0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I1 - DDPC_HPD1 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I2 - DDPD_HPD2 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I3 - DDPE_HPD3 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I4 - GPIO */
|
||||
PAD_CFG_GPI_INT(GPP_I4, NONE, PLTRST, OFF),
|
||||
/* GPP_I5 - DDPB_CTRLCLK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I6 - DDPB_CTRLDATA */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I6, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I7 - DDPC_CTRLCLK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I8 - DDPC_CTRLDATA */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I8, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I9 - DDPD_CTRLCLK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_I10 - DDPD_CTRLDATA */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_I10, 20K_PD, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
/* Early pad configuration in romstage */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* GPIO Group GPP_A */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
|
||||
/* ---- */
|
||||
/* SUSWARN#/SUSPWRDNACK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025),
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
/* GPP_A0 - RCIN# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_A1 - LAD0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A1, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_A2 - LAD1 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A2, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_A3 - LAD2 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A3, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_A4 - LAD3 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A4, 20K_PU, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
/* GPP_A5 - LFRAME# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_A6 - SERIRQ */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, PLTRST, NF1, NO_DISABLE, OFF),
|
||||
|
||||
/* GPP_A8 - CLKRUN# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, PLTRST, NF1, TX_DISABLE, OFF),
|
||||
/* GPP_A9 - CLKOUT_LPC0 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A9, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_A10 - CLKOUT_LPC1 */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A10, 20K_PD, PLTRST, NF1, RX_DISABLE, OFF),
|
||||
|
||||
/* GPP_A13 - SUSWARN#/SUSPWRDNACK */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_A14 - SUS_STAT# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, RX_DISABLE, OFF),
|
||||
/* GPP_A15 - SUS_ACK# */
|
||||
PAD_CFG_NF_BUF_TRIG(GPP_A15, 20K_PU, DEEP, NF1, TX_DISABLE, OFF),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue