mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working: - TianoCore - NVMe, SATA3 - USB2, USB3 - Thunderbolt - Graphics (GOP and libgfxinit) - Sound - Webcam - WLAN, LAN, Bluetooth, LTE - Keyboard, touchpad - TPM - flashrom support; reading / flashing from Linux - ACPI S3 WIP: - Documentation Not working: - EC ACPI (e.g. Fn keys, battery and power information) Boots Arch Linux (Linux 5.8.12) successfully. Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513 Signed-off-by: Felix Singer <felixsinger@posteo.net> Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer
Michael Niewöhner
parent
3622c0bf10
commit
d959a20114
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# Clevo N130WU
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## Hardware
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### Technology
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```eval_rst
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+------------------+--------------------------------+
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| CPU | Intel i7-8550U |
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+------------------+--------------------------------+
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| PCH | Intel Sunrise Point LP |
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+------------------+--------------------------------+
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| EC / Super IO | ITE IT8587E |
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+------------------+--------------------------------+
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| Coprocessor | Intel ME |
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+------------------+--------------------------------+
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```
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### Flash chip
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```eval_rst
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+---------------------+-----------------+
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| Type | Value |
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+=====================+=================+
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| Model | GD25Q64B |
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+---------------------+-----------------+
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| Socketed flash | no |
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+---------------------+-----------------+
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| Size | 8 MiB |
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+---------------------+-----------------+
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| In circuit flashing | Yes |
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+---------------------+-----------------+
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| Package | SOIC-8 |
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+---------------------+-----------------+
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| Write protection | No |
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+---------------------+-----------------+
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| Dual BIOS feature | No |
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+---------------------+-----------------+
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| Internal flashing | Yes |
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+---------------------+-----------------+
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```
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## Board status
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### Working
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### Not Working
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### Work in progress
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### Untested
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## Also known as
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* TUXEDO InfinityBook Pro 13 v3
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@ -26,6 +26,10 @@ This section contains documentation about coreboot on specific mainboards.
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- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
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## Clevo
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- [N130WU / N131WU](clevo/n130wu/index.md)
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## Dell
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- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_CLEVO_N130WU
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select EC_ACPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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# select HAVE_CMOS_DEFAULT
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# select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_KABYLAKE
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config VBOOT
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select VBOOT_NO_BOARD_SUPPORT
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select GBB_FLAG_DISABLE_LID_SHUTDOWN
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select GBB_FLAG_DISABLE_FWMP
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config MAINBOARD_DIR
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string
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default "clevo/kbl-u"
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config VARIANT_DIR
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string
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default "n13xwu" if BOARD_CLEVO_N130WU
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config MAINBOARD_PART_NUMBER
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string
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default "N130WU" if BOARD_CLEVO_N130WU
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config CBFS_SIZE
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hex
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default 0x600000 if BOARD_CLEVO_N130WU
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config DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
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config FMDFILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd" if VBOOT && !VBOOT_SLOTS_RW_A
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# TODO
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# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
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# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB
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config MAX_CPUS
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int
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default 8
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config DIMM_MAX
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int
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default 2
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config DIMM_SPD_SIZE
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int
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default 512
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config VGA_BIOS_ID
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string
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default "8086,5917" if BOARD_CLEVO_N130WU
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config PXE_ROM_ID
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string
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default "10ec,8168"
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config UART_FOR_CONSOLE
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int
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default 2
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config POST_DEVICE
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bool
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default n
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config CONSOLE_POST
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bool
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default y
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config LINEAR_FRAMEBUFFER_MAX_WIDTH
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int
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default 1920
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config LINEAR_FRAMEBUFFER_MAX_HEIGHT
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int
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default 1080
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endif
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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comment "Kaby Lake U"
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config BOARD_CLEVO_N130WU
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bool "N130WU / N131WU"
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/pc80/pc/ps2_controller.asl>
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Vendor name: Clevo
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Category: laptop
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Release year: 2018
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <mainboard/gpio.h>
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void bootblock_mainboard_early_init(void)
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{
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mainboard_configure_gpios();
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 // OEM revision
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)
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{
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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#include <cpu/intel/common/acpi/cpu.asl>
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Device (\_SB.PCI0) {
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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void mainboard_configure_gpios(void);
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#endif
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/ramstage.h>
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/*
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* TODO:
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* - Add kill switches for WLAN, BT, LTE, CCD
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* - Add support for WoL (LAN, WLAN)
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* - Make M.2 port configurable (SATA <> PCIe)
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* - Make SATA DevSlp configurable
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* - Make TBT port configurable (TBT <> DisplayPort)
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*/
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void mainboard_silicon_init_params(FSP_SIL_UPD *params)
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{
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mainboard_configure_gpios();
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/romstage.h>
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#include <spd_bin.h>
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#include <string.h>
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static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
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{
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const u16 RcompResistor[3] = {121, 81, 100};
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memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
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}
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static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
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{
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const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
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memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
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}
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG *mem_cfg;
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struct spd_block blk = {
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.addr_map = {0x50, 0x52},
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};
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mem_cfg = &mupd->FspmConfig;
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get_spd_smbus(&blk);
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dump_spd_info(&blk);
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mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
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mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
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mem_cfg->DqPinsInterleaved = TRUE;
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mem_cfg->MemorySpdDataLen = blk.len;
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mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
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mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
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}
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@ -0,0 +1 @@
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Board name: N130WU / N131WU
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Binary file not shown.
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@ -0,0 +1,166 @@
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/intel/skylake
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register "gpu_pp_up_delay_ms" = "200" # T3
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register "gpu_pp_down_delay_ms" = " 0" # T10
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register "gpu_pp_cycle_delay_ms" = "500" # T12
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register "gpu_pp_backlight_on_delay_ms" = " 50" # T7
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register "gpu_pp_backlight_off_delay_ms" = " 0" # T9
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register "gpu_pch_backlight_pwm_hz" = "200"
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# IGD Displays
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register "gfx" = "GMA_STATIC_DISPLAYS(0)"
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# FSP Configuration
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register "SkipExtGfxScan" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "eist_enable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "3" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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register "power_limits_config" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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}"
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x1313 inherit
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA thermal subsystem
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device pci 05.0 off end # Imaging Unit
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device pci 08.0 on end # Gaussian Mixture Model
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device pci 13.0 off end # Sensor Hub
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device pci 14.0 on # USB xHCI
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register "SsicPortEnable" = "0"
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
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register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right
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register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left
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register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 14.3 off end # Camera
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device pci 15.0 off end # I2C0
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device pci 15.1 off end # I2C1
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device pci 15.2 off end # I2C2
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device pci 15.3 off end # I2C3
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device pci 16.0 on # Management Engine Interface 1
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register "HeciEnabled" = "1"
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on # SATA
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register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
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register "SataSalpSupport" = "0"
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# Ports
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[2]" = "1"
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end
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device pci 19.0 on end # UART 2
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device pci 19.1 off end # I2C5
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device pci 19.2 off end # I2C4
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device pci 1c.0 on # PCI Express Port 1
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device pci 00.0 on end # x4 TBT
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register "PcieRpEnable[0]" = "1"
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "4"
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register "PcieRpClkSrcNumber[0]" = "4"
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register "PcieRpHotPlug[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
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end
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on # PCI Express Port 5
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device pci 00.0 on end # x1 LAN
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqNumber[4]" = "3"
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register "PcieRpClkSrcNumber[4]" = "3"
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register "PcieRpLtrEnable[4]" = "1"
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end
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device pci 1c.5 on # PCI Express Port 6
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device pci 00.0 on end # x1 WLAN
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register "PcieRpEnable[5]" = "1"
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register "PcieRpClkReqSupport[5]" = "1"
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register "PcieRpClkReqNumber[5]" = "2"
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register "PcieRpClkSrcNumber[5]" = "2"
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register "PcieRpLtrEnable[5]" = "1"
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smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
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end
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on # PCI Express Port 9
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device pci 00.0 on end # x4 M.2/M (J_SSD1)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "5"
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register "PcieRpClkSrcNumber[8]" = "5"
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register "PcieRpLtrEnable[8]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
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end
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 off end # UART 0
|
||||
device pci 1e.1 off end # UART 1
|
||||
device pci 1e.2 off end # GSPI 0
|
||||
device pci 1e.3 off end # GSPI 1
|
||||
device pci 1e.4 off end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 off end # SDXC
|
||||
device pci 1f.0 on # LPC Interface
|
||||
register "gen1_dec" = "0x000c0681"
|
||||
register "gen2_dec" = "0x000c1641"
|
||||
register "gen3_dec" = "0x000c0081"
|
||||
register "gen4_dec" = "0x00040069"
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 hidden end # P2SB
|
||||
device pci 1f.2 on # Power Management Controller
|
||||
register "gpe0_dw0" = "GPP_C"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
end
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
device pci 1f.7 off end # Trace Hub
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
FLASH 8M {
|
||||
SI_ALL@0x0 0x200000 {
|
||||
SI_DESC@0x0 0x1000
|
||||
SI_ME@0x1000 0x1ff000
|
||||
}
|
||||
SI_BIOS@0x200000 0x600000 {
|
||||
MISC_RW@0x0 0x2d000 {
|
||||
UNIFIED_MRC_CACHE@0x0 0x21000 {
|
||||
RECOVERY_MRC_CACHE@0x0 0x10000
|
||||
RW_MRC_CACHE@0x10000 0x10000
|
||||
RW_VAR_MRC_CACHE@0x20000 0x1000
|
||||
}
|
||||
RW_SHARED@0x21000 0x4000 {
|
||||
SHARED_DATA@0x0 0x2000
|
||||
VBLOCK_DEV@0x2000 0x2000
|
||||
}
|
||||
RW_VPD(PRESERVE)@0x25000 0x2000
|
||||
RW_NVRAM(PRESERVE)@0x27000 0x5000
|
||||
FPF_STATUS@0x2c000 0x1000
|
||||
}
|
||||
WP_RO@0x2d000 0x5d3000 {
|
||||
FMAP@0x0 0x800
|
||||
RO_VPD(PRESERVE)@0x800 0x4000
|
||||
RO_SECTION@0x4800 0x5ce800 {
|
||||
RO_FRID@0x0 0x40
|
||||
RO_FRID_PAD@0x40 0x7c0
|
||||
GBB@0x800 0x40000
|
||||
COREBOOT(CBFS)@0x40800 0x58e000
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(eDP,
|
||||
DP1,
|
||||
DP2,
|
||||
DP3,
|
||||
HDMI1,
|
||||
HDMI2,
|
||||
HDMI3,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,503 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
// RCIN#
|
||||
_PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0),
|
||||
|
||||
// LAD0
|
||||
_PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0),
|
||||
|
||||
// LAD1
|
||||
_PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0),
|
||||
|
||||
// LAD2
|
||||
_PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0),
|
||||
|
||||
// LAD3
|
||||
_PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0),
|
||||
|
||||
// LFRAME#
|
||||
_PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0),
|
||||
|
||||
// SERIRQ
|
||||
_PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0),
|
||||
|
||||
// PIRQA#
|
||||
_PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0),
|
||||
|
||||
// CLKRUN#
|
||||
_PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0),
|
||||
|
||||
// CLKOUT_LPC0
|
||||
_PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0),
|
||||
|
||||
// CLKOUT_LPC1
|
||||
_PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000),
|
||||
|
||||
// PME#
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0),
|
||||
|
||||
// BM_BUSY#
|
||||
_PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0),
|
||||
|
||||
// SUSWARN#/SUSPWRDNACK
|
||||
_PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0),
|
||||
|
||||
// SUS_STAT#/ESPI_RESET#
|
||||
_PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0),
|
||||
|
||||
// SUS_ACK#
|
||||
_PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0),
|
||||
|
||||
// SD_1P8_SEL
|
||||
_PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0),
|
||||
|
||||
// SD_PWR_EN#
|
||||
_PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0),
|
||||
|
||||
// ISH_GP0
|
||||
_PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0),
|
||||
|
||||
// ISH_GP1
|
||||
_PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0),
|
||||
|
||||
// ISH_GP2
|
||||
_PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0),
|
||||
|
||||
// ISH_GP3
|
||||
_PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000),
|
||||
|
||||
// ISH_GP4
|
||||
_PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0),
|
||||
|
||||
// ISH_GP5
|
||||
_PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0),
|
||||
|
||||
// CORE_VID0
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
|
||||
|
||||
// CORE_VID1
|
||||
_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
|
||||
|
||||
// VRALERT#
|
||||
_PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0),
|
||||
|
||||
// CPU_GP2
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0),
|
||||
|
||||
// CPU_GP3
|
||||
_PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0),
|
||||
|
||||
// SRCCLKREQ0#
|
||||
_PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0),
|
||||
|
||||
// SRCCLKREQ1#
|
||||
_PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0),
|
||||
|
||||
// SRCCLKREQ2#
|
||||
_PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0),
|
||||
|
||||
// SRCCLKREQ3#
|
||||
_PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0),
|
||||
|
||||
// SRCCLKREQ4#
|
||||
_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0),
|
||||
|
||||
// SRCCLKREQ5#
|
||||
_PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0),
|
||||
|
||||
// EXT_PWR_GATE#
|
||||
_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
|
||||
|
||||
// SLP_S0#
|
||||
_PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0),
|
||||
|
||||
// PLTRST#
|
||||
_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
|
||||
|
||||
// SPKR
|
||||
_PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000),
|
||||
|
||||
// GSPI0_CS#
|
||||
_PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0),
|
||||
|
||||
// GSPI0_CLK
|
||||
_PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0),
|
||||
|
||||
// GSPI0_MISO
|
||||
_PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0),
|
||||
|
||||
// GSPI0_MOSI
|
||||
_PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000),
|
||||
|
||||
// GSPI1_CS#
|
||||
_PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0),
|
||||
|
||||
// GSPI1_CLK
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0),
|
||||
|
||||
// GSPI1_MISO
|
||||
_PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0),
|
||||
|
||||
// GSPI1_MOSI
|
||||
_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
|
||||
|
||||
// SML1ALERT#/PCHHOT#
|
||||
_PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0),
|
||||
|
||||
// SMBCLK
|
||||
_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
|
||||
|
||||
// SMBDATA
|
||||
_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
|
||||
|
||||
// SMBALERT#
|
||||
_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
|
||||
|
||||
// SML0CLK
|
||||
_PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0),
|
||||
|
||||
// SML0DATA
|
||||
_PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0),
|
||||
|
||||
// SML0ALERT#
|
||||
_PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0),
|
||||
|
||||
// SML1CLK
|
||||
// _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
|
||||
|
||||
// SML1DATA
|
||||
// _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
|
||||
|
||||
// UART0_RXD
|
||||
_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0),
|
||||
|
||||
// UART0_TXD
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
|
||||
|
||||
// UART0_RTS#
|
||||
_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
|
||||
|
||||
// UART0_CTS#
|
||||
_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0),
|
||||
|
||||
// UART1_RXD
|
||||
_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
|
||||
|
||||
// UART1_TXD
|
||||
_PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0),
|
||||
|
||||
// UART1_RTS#
|
||||
_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
|
||||
|
||||
// UART1_CTS#
|
||||
_PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0),
|
||||
|
||||
// I2C0_SDA
|
||||
_PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0),
|
||||
|
||||
// I2C0_SCL
|
||||
_PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0),
|
||||
|
||||
// I2C1_SDA
|
||||
_PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0),
|
||||
|
||||
// I2C1_SCL
|
||||
_PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0),
|
||||
|
||||
// UART2_RXD
|
||||
_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
|
||||
|
||||
// UART2_TXD
|
||||
_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
|
||||
|
||||
// UART2_RTS#
|
||||
_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
|
||||
|
||||
// UART2_CTS#
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0),
|
||||
|
||||
// SPI1_CS#
|
||||
_PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0),
|
||||
|
||||
// SPI1_CLK
|
||||
_PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0),
|
||||
|
||||
// SPI1_MISO
|
||||
_PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0),
|
||||
|
||||
// SPI1_MOSI
|
||||
_PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0),
|
||||
|
||||
// FLASHTRIG
|
||||
_PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0),
|
||||
|
||||
// ISH_I2C0_SDA
|
||||
_PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0),
|
||||
|
||||
// ISH_I2C0_SCL
|
||||
_PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0),
|
||||
|
||||
// ISH_I2C1_SDA
|
||||
_PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0),
|
||||
|
||||
// ISH_I2C1_SCL
|
||||
_PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0),
|
||||
|
||||
// ISH_UART0_RXD
|
||||
_PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0),
|
||||
|
||||
// ISH_UART0_TXD
|
||||
_PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0),
|
||||
|
||||
// ISH_UART0_RTS#
|
||||
_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
|
||||
|
||||
// ISH_UART0_CTS#
|
||||
_PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0),
|
||||
|
||||
// DMIC_CLK1
|
||||
_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
|
||||
|
||||
// DMIC_DATA1
|
||||
_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0),
|
||||
|
||||
// DMIC_CLK0
|
||||
_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
|
||||
|
||||
// DMIC_DATA0
|
||||
_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0),
|
||||
|
||||
// SPI1_IO2
|
||||
_PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0),
|
||||
|
||||
// SPI1_IO3
|
||||
_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
|
||||
|
||||
// I2S_MCLK
|
||||
_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
|
||||
|
||||
// SATAXPCIE0/SATAGP0
|
||||
_PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000),
|
||||
|
||||
// SATAXPCIE1/SATAGP1
|
||||
_PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0),
|
||||
|
||||
// SATAXPCIE2/SATAGP2
|
||||
_PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0),
|
||||
|
||||
// CPU_GP0
|
||||
_PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0),
|
||||
|
||||
// DEVSLP0
|
||||
_PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0),
|
||||
|
||||
// DEVSLP1
|
||||
_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
|
||||
|
||||
// DEVSLP2
|
||||
_PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0),
|
||||
|
||||
// CPU_GP1
|
||||
_PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0),
|
||||
|
||||
// SATALED#
|
||||
_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
|
||||
|
||||
// USB2_OC0#
|
||||
_PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0),
|
||||
|
||||
// USB2_OC1#
|
||||
_PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0),
|
||||
|
||||
// USB2_OC2#
|
||||
_PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0),
|
||||
|
||||
// USB2_OC3#
|
||||
_PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0),
|
||||
|
||||
// DDPB_HPD0
|
||||
_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
|
||||
|
||||
// DDPC_HPD1
|
||||
_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
|
||||
|
||||
// DDPD_HPD2
|
||||
_PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0),
|
||||
|
||||
// DDPE_HPD3
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0),
|
||||
|
||||
// EDP_HPD
|
||||
_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
|
||||
|
||||
// DDPB_CTRLCLK
|
||||
_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0),
|
||||
|
||||
// DDPB_CTRLDATA
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
|
||||
|
||||
// DDPC_CTRLCLK
|
||||
_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0),
|
||||
|
||||
// DDPC_CTRLDATA
|
||||
_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
|
||||
|
||||
// DDPD_CTRLCLK
|
||||
_PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0),
|
||||
|
||||
// DDPD_CTRLDATA
|
||||
_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
|
||||
|
||||
// BATLOW#
|
||||
_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0),
|
||||
|
||||
// LANPHYPC
|
||||
_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0),
|
||||
|
||||
// LAN_WAKE#
|
||||
_PAD_CFG_STRUCT(GPD2, 0x880502, 0x0),
|
||||
|
||||
// PWRBTN#
|
||||
_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
|
||||
|
||||
// SLP_S3#
|
||||
_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
|
||||
|
||||
// SLP_S4#
|
||||
_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
|
||||
|
||||
// SLP_A#
|
||||
_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0),
|
||||
|
||||
// RSVD
|
||||
_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0),
|
||||
|
||||
// SUSCLK
|
||||
_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
|
||||
|
||||
// SLP_WLAN#
|
||||
_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0),
|
||||
|
||||
// SLP_S5#
|
||||
_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
|
||||
|
||||
// LANPHYPC
|
||||
_PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0),
|
||||
|
||||
// I2S2_SCLK
|
||||
_PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0),
|
||||
|
||||
// I2S2_SFRM
|
||||
_PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0),
|
||||
|
||||
// I2S2_TXD
|
||||
_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
|
||||
|
||||
// I2S2_RXD
|
||||
_PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0),
|
||||
|
||||
// I2C2_SDA
|
||||
_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C2_SCL
|
||||
_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C3_SDA
|
||||
_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C3_SCL
|
||||
_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C4_SDA
|
||||
_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C4_SCL
|
||||
_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000),
|
||||
|
||||
// I2C5_SDA/ISH_I2C2_SDA
|
||||
_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000),
|
||||
|
||||
// I2C5_SCL/ISH_I2C2_SCL
|
||||
_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000),
|
||||
|
||||
// EMMC_CMD
|
||||
_PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA0
|
||||
_PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA1
|
||||
_PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA2
|
||||
_PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA3
|
||||
_PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA4
|
||||
_PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA5
|
||||
_PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA6
|
||||
_PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_DATA7
|
||||
_PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_RCLK
|
||||
_PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0),
|
||||
|
||||
// EMMC_CLK
|
||||
_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
|
||||
|
||||
// GPIO
|
||||
_PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0),
|
||||
|
||||
// SD_CMD
|
||||
_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
|
||||
|
||||
// SD_DATA0
|
||||
_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0),
|
||||
|
||||
// SD_DATA1
|
||||
_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
|
||||
|
||||
// SD_DATA2
|
||||
_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
|
||||
|
||||
// SD_DATA3
|
||||
_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
|
||||
|
||||
// SD_CD#
|
||||
_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0),
|
||||
|
||||
// SD_CLK
|
||||
_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
|
||||
|
||||
// SD_WP
|
||||
_PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0)
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
// UART2_RXD
|
||||
_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
|
||||
|
||||
// UART2_TXD
|
||||
_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0)
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek ALC269VC */
|
||||
0x10ec0269,
|
||||
0x15581314,
|
||||
11,
|
||||
AZALIA_SUBVENDOR(0, 0x15581314),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170120),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211010),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
|
||||
/* Intel iGPU HDMI */
|
||||
0x8086280b,
|
||||
0x80860101,
|
||||
4,
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
AZALIA_PIN_CFG(2, 0x5, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x6, 0x18560010),
|
||||
AZALIA_PIN_CFG(2, 0x7, 0x18560010)
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
Loading…
Reference in New Issue