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mb/google/nissa/var/craaskov: Configure GPIOs according to schematics 

Configure GPIOs based on schematics and confirm with EE.

BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot

Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Rex Chou 2023-07-20 14:00:24 +08:00 committed by Eric Lai
parent 7333901701
commit d97d860f23
2 changed files with 82 additions and 0 deletions
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4
src/mainboard/google/brya/variants/craaskov/Makefile.inc Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
bootblock-y += gpio.c
ramstage-y += gpio.c

78
src/mainboard/google/brya/variants/craaskov/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <soc/gpio.h>
/* Pad configuration in ramstage */
static const struct pad_config override_gpio_table[] = {
/* A21 : GPP_A21 ==> NC */
PAD_NC(GPP_A21, NONE),
/* A21 : GPP_A22 ==> NC */
PAD_NC(GPP_A22, NONE),
/* B5 : I2C2_SDA ==> TOF_I2C_DAT */
PAD_CFG_NF_LOCK(GPP_B5, NONE, NF1, LOCK_CONFIG),
/* B6 : I2C2_SCL ==> TOF_I2C_CLK */
PAD_CFG_NF_LOCK(GPP_B6, NONE, NF1, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NC */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D8 : SRCCLKREQ3# ==> NC */
PAD_NC(GPP_D8, NONE),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE),
/* F13 : SOC_PEN_DETECT_R_ODL ==> NC */
PAD_NC(GPP_F13, NONE),
/* F15 : SOC_PEN_DETECT_ODL ==> NC */
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
/* H8 : CNV_MFUART2_RXD ==> NC */
PAD_NC(GPP_H8, NONE),
/* H9 : CNV_MFUART2_TXD ==> NC */
PAD_NC(GPP_H9, NONE),
/* H12 : UART0_RTS# ==> NC */
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H13 : UART0_CTS# ==> NC */
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
/* H19 : SRCCLKREQ4# ==> TOF_INT# */
PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, EDGE_BOTH),
/* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE),
/* R6 : DMIC_CLK_A_1A ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_DATA_1A ==> NC */
PAD_NC(GPP_R7, NONE),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
return override_gpio_table;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}