mb/google/mancomb: Enable some PCIe power saving features
Enable ASPM, Common Clock and Clock Power Managment. Accomplish this by adding the options in the platform Kconfig as well as dxio descriptors. BUG=b:187743927 TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci Change-Id: I9d6e606763798afc6b797d7d24ee7cae09f9e33f Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54681 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -28,6 +28,9 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_I2C_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PSP_DISABLE_POSTCODES
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select SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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@ -12,6 +12,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
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.end_logical_lane = 0,
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.device_number = 2,
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.function_number = 1,
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.link_aspm = ASPM_L1,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ0,
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.gpio_group_id = GPIO_29,
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@ -24,6 +25,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
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.end_logical_lane = 1,
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.device_number = 2,
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.function_number = 2,
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.link_aspm = ASPM_L1,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ1,
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.gpio_group_id = GPIO_70,
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@ -36,6 +38,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
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.end_logical_lane = 2,
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.device_number = 2,
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.function_number = 3,
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.link_aspm = ASPM_L1,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ2,
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.gpio_group_id = GPIO_18,
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@ -48,6 +51,7 @@ static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = {
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.end_logical_lane = 7,
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.device_number = 2,
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.function_number = 4,
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.link_aspm = ASPM_L1,
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.turn_off_unused_lanes = true,
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.clk_req = CLK_REQ3,
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.gpio_group_id = GPIO_40,
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