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mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L 

In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant
is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default
and only overriding to GPIO_70 for guybrush bid==1.

BUG=b:202992077
BRANCH=None
TEST=Build and boot guybrush, SD card works

Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Rob Barnes 2021-11-09 10:34:10 -07:00 committed by Karthik Ramasubramanian
parent aba1c13581
commit da0c4f42f6
6 changed files with 19 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/google/guybrush/variants/baseboard/gpio.c
View File

@ -21,8 +21,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPO(GPIO_3, LOW), PAD_GPO(GPIO_3, LOW),
/* SOC_PEN_DETECT_ODL */ /* SOC_PEN_DETECT_ODL */
PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3),
/* SD_AUX_RESET_L */ /* Unused */
PAD_GPO(GPIO_5, HIGH), PAD_NC(GPIO_5),
/* EN_PP3300_WLAN */ /* EN_PP3300_WLAN */
PAD_GPO(GPIO_6, HIGH), PAD_GPO(GPIO_6, HIGH),
/* EN_PP3300_TCHPAD */ /* EN_PP3300_TCHPAD */
@ -81,8 +81,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPI(GPIO_67, PULL_NONE), PAD_GPI(GPIO_67, PULL_NONE),
/* EN_PP3300_TCHSCR */ /* EN_PP3300_TCHSCR */
PAD_GPO(GPIO_68, HIGH), PAD_GPO(GPIO_68, HIGH),
/* Unused */ /* SD_AUX_RESET_L */
PAD_NC(GPIO_69), PAD_GPO(GPIO_69, HIGH),
/* Unused TP27 */ /* Unused TP27 */
PAD_NC(GPIO_70), PAD_NC(GPIO_70),
/* GPIO_71 - GPIO_73: Not available */ /* GPIO_71 - GPIO_73: Not available */
@ -170,16 +170,16 @@ static const struct soc_amd_gpio base_gpio_table[] = {
/* Early GPIO configuration */ /* Early GPIO configuration */
static const struct soc_amd_gpio early_gpio_table[] = { static const struct soc_amd_gpio early_gpio_table[] = {
/* Assert all AUX reset lines */ /* Assert all AUX reset lines */
/* SD_AUX_RESET_L */ /* Unused */
PAD_GPO(GPIO_5, LOW), PAD_NC(GPIO_5),
/* WWAN_AUX_RESET_L */ /* WWAN_AUX_RESET_L */
PAD_GPO(GPIO_18, LOW), PAD_GPO(GPIO_18, LOW),
/* WLAN_AUX_RESET (ACTIVE HIGH) */ /* WLAN_AUX_RESET (ACTIVE HIGH) */
PAD_GPO(GPIO_29, HIGH), PAD_GPO(GPIO_29, HIGH),
/* SSD_AUX_RESET_L */ /* SSD_AUX_RESET_L */
PAD_GPO(GPIO_40, LOW), PAD_GPO(GPIO_40, LOW),
/* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ /* SD_AUX_RESET_L */
PAD_NC(GPIO_69), PAD_GPO(GPIO_69, LOW),
/* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */
PAD_NC(GPIO_70), PAD_NC(GPIO_70),
@ -278,16 +278,16 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
/* PCIE_RST needs to be brought high before FSP-M runs */ /* PCIE_RST needs to be brought high before FSP-M runs */
static const struct soc_amd_gpio pcie_gpio_table[] = { static const struct soc_amd_gpio pcie_gpio_table[] = {
/* Deassert all AUX_RESET lines & PCIE_RST */ /* Deassert all AUX_RESET lines & PCIE_RST */
/* SD_AUX_RESET_L */ /* Unused */
PAD_GPO(GPIO_5, HIGH), PAD_NC(GPIO_5),
/* WWAN_AUX_RESET_L */ /* WWAN_AUX_RESET_L */
PAD_GPO(GPIO_18, HIGH), PAD_GPO(GPIO_18, HIGH),
/* WLAN_AUX_RESET (ACTIVE HIGH) */ /* WLAN_AUX_RESET (ACTIVE HIGH) */
PAD_GPO(GPIO_29, LOW), PAD_GPO(GPIO_29, LOW),
/* SSD_AUX_RESET_L */ /* SSD_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* Guybrush BID >= 2: SD_AUX_RESET_L, Other variants: Unused */ /* SD_AUX_RESET_L */
PAD_NC(GPIO_69), PAD_GPO(GPIO_69, HIGH),
/* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */ /* Guybrush BID>1, Other variants : Unused TP27; BID==1: SD_AUX_RESET_L */
PAD_NC(GPIO_70), PAD_NC(GPIO_70),
/* PCIE_RST0_L */ /* PCIE_RST0_L */

2
src/mainboard/google/guybrush/variants/baseboard/helpers.c
View File

@ -11,5 +11,5 @@ bool __weak variant_has_pcie_wwan(void)
uint8_t __weak variant_sd_aux_reset_gpio(void) uint8_t __weak variant_sd_aux_reset_gpio(void)
{ {
return GPIO_5; return GPIO_69;
} }

16
src/mainboard/google/guybrush/variants/guybrush/gpio.c
View File

@ -31,8 +31,6 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = {
/* EN_PP5000_PEN */ /* EN_PP5000_PEN */
PAD_GPO(GPIO_5, HIGH), PAD_GPO(GPIO_5, HIGH),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, HIGH),
/* GSC_SOC_INT_L */ /* GSC_SOC_INT_L */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* Unused */ /* Unused */
@ -42,9 +40,6 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = {
}; };
static const struct soc_amd_gpio override_early_gpio_table[] = { static const struct soc_amd_gpio override_early_gpio_table[] = {
PAD_NC(GPIO_5),
/* BID >= 2: SD_AUX_RESET_L */
PAD_GPO(GPIO_69, LOW),
/* BID == 1: SD_AUX_RESET_L */ /* BID == 1: SD_AUX_RESET_L */
PAD_GPO(GPIO_70, LOW), PAD_GPO(GPIO_70, LOW),
/* GSC_SOC_INT_L */ /* GSC_SOC_INT_L */
@ -55,18 +50,10 @@ static const struct soc_amd_gpio override_early_gpio_table[] = {
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
PAD_NC(GPIO_5),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_70, HIGH), PAD_GPO(GPIO_70, HIGH),
}; };
/* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid2_pcie_gpio_table[] = {
PAD_NC(GPIO_5),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, HIGH),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{ {
uint32_t board_version = board_id(); uint32_t board_version = board_id();
@ -101,6 +88,5 @@ const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
return bid1_pcie_gpio_table; return bid1_pcie_gpio_table;
} }
*size = ARRAY_SIZE(bid2_pcie_gpio_table); return NULL;
return bid2_pcie_gpio_table;
} }

3
src/mainboard/google/guybrush/variants/guybrush/variant.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <boardid.h>
#include <device/device.h> #include <device/device.h>
#include <soc/gpio.h> #include <soc/gpio.h>
@ -11,5 +12,5 @@ bool variant_has_pcie_wwan(void)
uint8_t variant_sd_aux_reset_gpio(void) uint8_t variant_sd_aux_reset_gpio(void)
{ {
return GPIO_69; return board_id() == 1 ? GPIO_70 : GPIO_69;
} }

29
src/mainboard/google/guybrush/variants/nipperkin/gpio.c
View File

@ -16,8 +16,6 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = {
PAD_NC(GPIO_18), PAD_NC(GPIO_18),
/* LCD_PRIVACY_PCH */ /* LCD_PRIVACY_PCH */
PAD_GPO(GPIO_5, HIGH), PAD_GPO(GPIO_5, HIGH),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, HIGH),
/* GSC_SOC_INT_L */ /* GSC_SOC_INT_L */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* Unused */ /* Unused */
@ -34,30 +32,16 @@ static const struct soc_amd_gpio bid2_override_gpio_table[] = {
PAD_NC(GPIO_17), PAD_NC(GPIO_17),
/* LCD_PRIVACY_PCH */ /* LCD_PRIVACY_PCH */
PAD_GPO(GPIO_18, HIGH), PAD_GPO(GPIO_18, HIGH),
/* Unused */
PAD_NC(GPIO_69),
}; };
static const struct soc_amd_gpio override_early_gpio_table[] = { static const struct soc_amd_gpio override_early_gpio_table[] = {
/* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */ /* BID == 1: GSC_SOC_INT_L, BID > 1: Unused */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
PAD_NC(GPIO_18), PAD_NC(GPIO_18),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, LOW),
}; };
/* This table is used by nipperkin variant with board version < 2. */ static const struct soc_amd_gpio override_pcie_gpio_table[] = {
static const struct soc_amd_gpio bid1_override_pcie_gpio_table[] = {
PAD_NC(GPIO_5),
PAD_NC(GPIO_18), PAD_NC(GPIO_18),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, HIGH),
};
/* This table is used by nipperkin variant with board version >= 2. */
static const struct soc_amd_gpio bid2_override_pcie_gpio_table[] = {
PAD_NC(GPIO_18),
PAD_NC(GPIO_69),
}; };
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
@ -81,13 +65,6 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
{ {
uint32_t board_version = board_id(); *size = ARRAY_SIZE(override_pcie_gpio_table);
return override_pcie_gpio_table;
if (board_version < 2) {
*size = ARRAY_SIZE(bid1_override_pcie_gpio_table);
return bid1_override_pcie_gpio_table;
}
*size = ARRAY_SIZE(bid2_override_pcie_gpio_table);
return bid2_override_pcie_gpio_table;
} }

7
src/mainboard/google/guybrush/variants/nipperkin/variant.c
View File

@ -10,10 +10,3 @@ void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors)
dxio_descriptors[WLAN].link_aspm_L1_1 = false; dxio_descriptors[WLAN].link_aspm_L1_1 = false;
dxio_descriptors[WLAN].link_aspm_L1_2 = false; dxio_descriptors[WLAN].link_aspm_L1_2 = false;
} }
uint8_t variant_sd_aux_reset_gpio(void)
{
uint32_t board_ver = board_id();
return (board_ver < 2) ? GPIO_69 : GPIO_5;
}