mb/ocp/wedge100s: Use the new IPMI driver

* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address

Tested on Wedge100s.

Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/ocp/wedge100s/Kconfig

@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_TPM1
 	select DRIVERS_UART_8250IO
 	select SUPERIO_ITE_IT8528E
+	select IPMI_KCS
 
 config VBOOT
 	select VBOOT_VBNV_CMOS

src/mainboard/ocp/wedge100s/devicetree.cb

@@ -60,6 +60,9 @@ chip soc/intel/fsp_broadwell_de
 				device pnp 6e.18 off end
 				device pnp 6e.19 off end
 			end	#superio/ite/it8528e
+			chip drivers/ipmi
+				device pnp ca2.0 on end		# IPMI KCS
+			end
 		end # LPC Bridge
 		device pci 1f.2 on end # SATA Controller
 		device pci 1f.3 on end # SMBus Controller

src/mainboard/ocp/wedge100s/romstage.c

@@ -38,6 +38,10 @@ void early_mainboard_romstage_entry(void)
 	pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
 			   (0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);
 
+	/* Decode IPMI KCS */
+	pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC,
+			   (0 << 16) | ALIGN_DOWN(0xca2, 4) | 1);
+
 	if (CONFIG(CONSOLE_SERIAL))
 		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);