soc/mediatek/mt8188: Support ARM arch timer
Use ARM architectual timer by initializing frequency to 13 MHz. Since system timer is the source of the architectual timer, we also call `timer_prepare` in `init_timer`. BUG=b:229800119 TEST=run `suite:faft_bios` to verify the firmware stability. check timestamps by cbmem. Cq-Depend: chromium:4747539 Change-Id: I8b1348044e4c92984510604b7f61611e13284d86 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8188
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select MEDIATEK_DRAM_BLOB_FAST_INIT
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select MEDIATEK_DRAM_BLOB_FAST_INIT
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select USE_CBMEM_DRAM_INFO
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select USE_CBMEM_DRAM_INFO
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select DPM_FOUR_CHANNEL
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select DPM_FOUR_CHANNEL
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select ARM64_USE_ARCH_TIMER
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if SOC_MEDIATEK_MT8188
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if SOC_MEDIATEK_MT8188
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@ -6,7 +6,7 @@ all-y += ../common/gpio.c ../common/gpio_op.c gpio.c
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all-y += ../common/i2c.c i2c.c
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all-y += ../common/i2c.c i2c.c
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all-y += ../common/pll.c pll.c
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all-y += ../common/pll.c pll.c
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all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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all-y += ../common/timer.c ../common/timer_prepare.c
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all-y += timer.c ../common/timer_prepare.c
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all-y += ../common/uart.c
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all-y += ../common/uart.c
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bootblock-y += bootblock.c
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bootblock-y += bootblock.c
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@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/lib_helpers.h>
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#include <commonlib/helpers.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/timer.h>
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static struct mtk_gpt_regs *const mtk_gpt = (void *)GPT_BASE;
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void init_timer(void)
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{
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timer_prepare();
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raw_write_cntfrq_el0(13 * MHz);
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/* TODO: remove GPT timer init after DRAM blob switching to arch timer */
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/* Disable timer and clear the counter */
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clrbits32(&mtk_gpt->gpt6_con, GPT6_CON_EN);
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setbits32(&mtk_gpt->gpt6_con, GPT6_CON_CLR);
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/* Set clock source to system clock and set clock divider to 1 */
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SET32_BITFIELDS(&GPT6_CLOCK_REG(mtk_gpt),
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GPT6_CLK_CLK6, GPT6_CLK_CLK6_SYS,
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GPT6_CLK_CLKDIV6, GPT6_CLK_CLKDIV_DIV1);
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/* Set operation mode to FREERUN mode and enable timer */
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SET32_BITFIELDS(&mtk_gpt->gpt6_con,
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GPT6_CON_MODE6, GPT6_MODE_FREERUN,
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GPT6_CON_EN6, GPT6_CON_EN);
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}
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