soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC
BUG=chrome-os-partner:49249 chrome-os-partner:50928 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: a48131897217a6e48927d5aafc855a86551c35ca Original-Change-Id: Ia7bab63e5abfb99ab0c03e0e2879149597b7355f Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333294 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add Kconfig option for SBL binary path BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: 8f0899e3c69737ec7ba579979dae342673bf3962 Original-Change-Id: If199f755106dc58b55ee0499e05304f0ea117bee Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333307 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> soc/qualcomm/ipq40xx: Add rules to combine vendor binary and CB binaries BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: d4b49d37c5b6f86a3bc360051904175111e1db2b Original-Change-Id: I85fde202213b47d5e7c9af3a8d920da20cf456fa Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333308 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I91b873894975f0a88babc2e2ecdbe5676ee17c0b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14649 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -22,13 +22,24 @@ config MBN_ENCAPSULATION
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bool "bootblock encapsulation for ipq40xx"
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default y
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config SBL_BLOB
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config CDT_MBN
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string "CDT binary blob"
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default "cdt-AP.DK01.1-C1.bin"
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config DDR_MBN
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string "DDR driver binary blob"
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default "ddr.mbn"
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config TZ_MBN
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string "TZ binary blob"
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default "tzbsp_no_xpu.mbn"
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config SBL_ELF
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depends on USE_BLOBS
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string "file name of the Qualcomm SBL blob"
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default "3rdparty/blobs/cpu/qualcomm/ipq40xx/uber-sbl.mbn"
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string "file name of the QCA SBL ELF"
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default "3rdparty/blobs/cpu/qualcomm/ipq40xx/sbl.elf"
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help
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The path and filename of the binary blob containing
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ipq40xx early initialization code, as supplied by the
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vendor.
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endif
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@ -52,25 +52,17 @@ ramstage-y += tz_wrapper.S
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ifeq ($(CONFIG_USE_BLOBS),y)
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# Add MBN header to allow SBL3 to start coreboot bootblock
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$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin
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@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
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./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp
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@mv $@.tmp $@
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# Create a complete bootblock which will start up the system
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$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \
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$(objcbfs)/bootblock.mbn
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@printf " MBNCAT $(subst $(obj)/,,$(@))\n"
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@util/ipqheader/mbncat.py -o $@.tmp $^
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@mv $@.tmp $@
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$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \
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$(objcbfs)/bootblock.elf
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@printf " CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n"
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@util/ipqheader/createxbl.py -f $(CONFIG_SBL_ELF) -s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32
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endif
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CPPFLAGS_common += -Isrc/soc/qualcomm/ipq40xx/include
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# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC
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mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
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mbn-files := $(CONFIG_CDT_MBN) $(CONFIG_DDR_MBN) $(CONFIG_TZ_MBN)
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# Location of the binary blobs
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mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq40xx
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