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Varadarajan Narayanan dc17d2de34 soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC
BUG=chrome-os-partner:49249 chrome-os-partner:50928
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Original-Commit-Id: a48131897217a6e48927d5aafc855a86551c35ca
Original-Change-Id: Ia7bab63e5abfb99ab0c03e0e2879149597b7355f
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333294
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

squashed:

soc/qualcomm/ipq40xx: Add Kconfig option for SBL binary path

BUG=chrome-os-partner:49249
TEST=Compiles...
BRANCH=none

Original-Commit-Id: 8f0899e3c69737ec7ba579979dae342673bf3962
Original-Change-Id: If199f755106dc58b55ee0499e05304f0ea117bee
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333307
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

soc/qualcomm/ipq40xx: Add rules to combine vendor binary and CB binaries

BUG=chrome-os-partner:49249
TEST=Compiles...
BRANCH=none

Original-Commit-Id: d4b49d37c5b6f86a3bc360051904175111e1db2b
Original-Change-Id: I85fde202213b47d5e7c9af3a8d920da20cf456fa
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333308
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I91b873894975f0a88babc2e2ecdbe5676ee17c0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14649
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10 21:35:30 +02:00
3rdparty 3rdparty/blobs: add more Qualcomm stubs 2016-05-10 21:22:28 +02:00
Documentation Documentation: x86 MTRR setup, TempRamExit and MTRR loading 2016-03-21 20:12:35 +01:00
payloads coreboot_tables: Extend serial port description 2016-05-09 17:21:22 +02:00
src soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoC 2016-05-10 21:35:30 +02:00
util util: ipq40xx: Scripts to combine SBL and Coreboot ELFs 2016-05-09 09:36:27 +02:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
MAINTAINERS MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boards 2016-04-19 19:25:59 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc xip: Do not pass --xip for early stages if CAR supports code execution 2016-05-09 05:01:58 +02:00
README README: improve description of compiler requirements 2015-07-30 05:11:33 +02:00
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.