intel/common/block/fast_spi: Add config option to disable write status
Chrome OS systems rely on the write status register to enable/disable flash write protection and disabling this opcode breaks the ability to enable or disable write protection with flashrom. Add a configure option for this feature that will disable the opcode for Write Status commands unless CONFIG_CHROMEOS is enabled. Tested to ensure that a default build without CONFIG_CHROMEOS has this option enabled while a build with CONFIG_CHROMEOS does not. Also ensured that when this option is disabled (for Chrome OS) then flashrom can be used with the --wp-enable and --wp-disable commands, depending on the state of the external write protect pin. Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/21021 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI
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bool
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help
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Intel Processor common FAST_SPI support
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config FAST_SPI_DISABLE_WRITE_STATUS
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bool "Disable write status SPI opcode"
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depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI
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default n if CHROMEOS
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default y
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help
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Disable the write status SPI opcode in Intel Fast SPI block.
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@ -144,7 +144,10 @@ void fast_spi_set_opcode_menu(void)
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void fast_spi_lock_bar(void)
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{
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void *spibar = fast_spi_get_bar();
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const uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_WRSDIS;
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uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;
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if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))
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hsfs |= SPIBAR_HSFSTS_WRSDIS;
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write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
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}
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