GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/common/block/fast_spi: Add config option to disable write status 

Chrome OS systems rely on the write status register to enable/disable
flash write protection and disabling this opcode breaks the ability
to enable or disable write protection with flashrom.

Add a configure option for this feature that will disable the opcode
for Write Status commands unless CONFIG_CHROMEOS is enabled.

Tested to ensure that a default build without CONFIG_CHROMEOS has this
option enabled while a build with CONFIG_CHROMEOS does not.  Also
ensured that when this option is disabled (for Chrome OS) then flashrom
can be used with the --wp-enable and --wp-disable commands, depending
on the state of the external write protect pin.

Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/21021
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Duncan Laurie 2017-08-15 13:32:26 -07:00
parent a102a029c5
commit dc1e6bc277
2 changed files with 12 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/common/block/fast_spi/Kconfig
View File

@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_FAST_SPI
bool bool
help help
Intel Processor common FAST_SPI support Intel Processor common FAST_SPI support
config FAST_SPI_DISABLE_WRITE_STATUS
bool "Disable write status SPI opcode"
depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI
default n if CHROMEOS
default y
help
Disable the write status SPI opcode in Intel Fast SPI block.

5
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -144,7 +144,10 @@ void fast_spi_set_opcode_menu(void)
void fast_spi_lock_bar(void) void fast_spi_lock_bar(void)
{ {
void *spibar = fast_spi_get_bar(); void *spibar = fast_spi_get_bar();
const uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN | SPIBAR_HSFSTS_WRSDIS; uint16_t hsfs = SPIBAR_HSFSTS_FLOCKDN;
if (IS_ENABLED(CONFIG_FAST_SPI_DISABLE_WRITE_STATUS))
hsfs |= SPIBAR_HSFSTS_WRSDIS;
write16(spibar + SPIBAR_HSFSTS_CTL, hsfs); write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
} }