sb/intel: Use ACPI_FADT_C2/C3_NOT_SUPPORTED defines
Change-Id: I242e05ee63f46bedbab3a425e922e60f1c749a15 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -32,8 +32,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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/* P_LVLx not used */
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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/* P_CNT not supported */
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fadt->duty_offset = 0;
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fadt->duty_width = 0;
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@ -36,8 +36,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 4;
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fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
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fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
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fadt->duty_width = 3; /* this width is in bits */
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fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
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@ -32,8 +32,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->pm_tmr_len = 4;
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fadt->gpe0_blk_len = 16;
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/* P_LVLx not used */
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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/* P_CNT not supported */
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fadt->duty_offset = 0;
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fadt->duty_width = 0;
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@ -45,8 +45,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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fadt->gpe0_blk_len = 2 * 8;
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/* P_LVLx not used */
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fadt->p_lvl2_lat = 101;
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fadt->p_lvl3_lat = 1001;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->duty_offset = 0;
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fadt->duty_width = 0;
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fadt->day_alrm = 0xd;
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