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nb/intel/i945: Move boilerplate romstage to a common location 

This adds callbacks for mainboard specific init.

Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-11-12 20:37:21 +01:00 committed by Patrick Georgi
parent bf53acca5e
commit dc584c3f22
13 changed files with 189 additions and 578 deletions
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57
src/mainboard/apple/macbook21/romstage.c
View File

@ -15,19 +15,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <arch/romstage.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* V0CTL Virtual Channel 0 Resource Control */ /* V0CTL Virtual Channel 0 Resource Control */
RCBA32(0x0014) = 0x80000001; RCBA32(0x0014) = 0x80000001;
@ -57,49 +48,3 @@ static void rcba_config(void)
RCBA32(0x1e9c) = 0x000200f0; RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801; RCBA32(0x1e98) = 0x000c0801;
} }
void mainboard_romstage_entry(void)
{
int s3resume = 0;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
enable_lapic();
i82801gx_lpc_setup();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n");
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}

61
src/mainboard/asus/p5gc-mx/romstage.c
View File

@ -19,16 +19,11 @@
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <console/console.h> #include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h> #include <cpu/intel/speedstep.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -96,65 +91,27 @@ static u8 msr_get_fsb(void)
return fsbcfg; return fsbcfg;
} }
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Enable PCIe Root Port Clock Gate */ /* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001; RCBA32(CG) = 0x00000001;
} }
void mainboard_romstage_entry(void)
void mainboard_pre_raminit_config(int s3_resume)
{ {
int s3resume = 0, boot_mode = 0;
u8 c_bsel = msr_get_fsb(); u8 c_bsel = msr_get_fsb();
enable_lapic();
i82801gx_lpc_setup();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* /*
* Result is that FSB is incorrect on s3 resume (fixed at 800MHz). * Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
* Some CPU accept this others don't. * Some CPU accept this others don't.
*/ */
if (!s3resume && setup_sio_gpio(c_bsel)) { if (!s3_resume && setup_sio_gpio(c_bsel)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Needs reset to configure CPU BSEL straps\n"); "Needs reset to configure CPU BSEL straps\n");
full_reset(); full_reset();
} }
}
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus(); void mainboard_superio_config(void)
{
if (CONFIG(DEBUG_RAM_SETUP)) winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

61
src/mainboard/getac/p470/romstage.c
View File

@ -16,22 +16,16 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <delay.h> #include <delay.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#include "option_table.h" #include "option_table.h"
static void setup_special_ich7_gpios(void) void mainboard_pre_raminit_config(int s3_resume)
{ {
u32 gpios; u32 gpios;
@ -52,7 +46,7 @@ static void setup_special_ich7_gpios(void)
} }
/* Override the default lpc decode ranges */ /* Override the default lpc decode ranges */
static void mb_lpc_decode(void) void mainboard_lpc_decode(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) if (read_option(lpt, 0) != 0)
@ -81,7 +75,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
outb(0xaa, port); outb(0xaa, port);
} }
static void early_superio_config(void) void mainboard_superio_config(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;
@ -126,7 +120,7 @@ static void early_superio_config(void)
pnp_exit_ext_func_mode(dev); pnp_exit_ext_func_mode(dev);
} }
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001; //RCBA32(0x0014) = 0x80000001;
@ -158,50 +152,3 @@ static void rcba_config(void)
RCBA32(0x1e9c) = 0x000200f0; RCBA32(0x1e9c) = 0x000200f0;
RCBA32(0x1e98) = 0x000c0801; RCBA32(0x1e98) = 0x000c0801;
} }
void mainboard_romstage_entry(void)
{
int s3resume = 0;
enable_lapic();
i82801gx_lpc_setup();
mb_lpc_decode();
early_superio_config();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
setup_special_ich7_gpios();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}

66
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
View File

@ -14,25 +14,17 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
#define SUPERIO_DEV PNP_DEV(0x2e, 0) #define SUPERIO_DEV PNP_DEV(0x2e, 0)
static void setup_sio(void) void mainboard_superio_config(void)
{ {
/* Set default GPIOs on superio */ /* Set default GPIOs on superio */
ite_reg_write(GPIO_DEV, 0x25, 0x40); ite_reg_write(GPIO_DEV, 0x25, 0x40);
@ -54,59 +46,15 @@ static void setup_sio(void)
ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
ite_reg_write(EC_DEV, 0x30, 0xff); // Enable ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
}
static void rcba_config(void)
{
/* Enable PCIe Root Port Clock Gate */
RCBA32(CG) = 0x00000001;
}
void mainboard_romstage_entry(void)
{
int s3resume = 0, boot_mode = 0;
enable_lapic();
i82801gx_lpc_setup();
/* Enable SuperIO PM */
setup_sio();
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Disable SIO reboot */ /* Disable SIO reboot */
ite_reg_write(GPIO_DEV, 0xEF, 0x7E); ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
}
/* Set up the console */
console_init(); void mainboard_late_rcba_config(void)
{
if (MCHBAR16(SSKPD) == 0xCAFE) { /* Enable PCIe Root Port Clock Gate */
printk(BIOS_DEBUG, "soft reset detected.\n"); RCBA32(CG) = 0x00000001;
boot_mode = 1;
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

55
src/mainboard/ibase/mb899/romstage.c
View File

@ -14,20 +14,13 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
#include <southbridge/intel/common/pmclib.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0) #define SUPERIO_DEV PNP_DEV(0x4e, 0)
@ -36,7 +29,7 @@
* Also set up the GPIOs from the beginning. This is the "no schematic * Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method. * but safe anyways" method.
*/ */
static void early_superio_config_w83627ehg(void) void mainboard_superio_config(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;
@ -103,7 +96,7 @@ static void early_superio_config_w83627ehg(void)
pnp_exit_conf_state(dev); pnp_exit_conf_state(dev);
} }
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001; //RCBA32(0x0014) = 0x80000001;
@ -123,47 +116,3 @@ static void rcba_config(void)
/* Enable PCIe Root Port Clock Gate */ /* Enable PCIe Root Port Clock Gate */
// RCBA32(0x341c) = 0x00000001; // RCBA32(0x341c) = 0x00000001;
} }
void mainboard_romstage_entry(void)
{
int s3resume = 0;
enable_lapic();
i82801gx_lpc_setup();
early_superio_config_w83627ehg();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}

52
src/mainboard/intel/d945gclf/romstage.c
View File

@ -13,22 +13,14 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h> #include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
//RCBA32(0x0014) = 0x80000001; //RCBA32(0x0014) = 0x80000001;
@ -47,49 +39,9 @@ static void rcba_config(void)
// RCBA32(0x341c) = 0x00000001; // RCBA32(0x341c) = 0x00000001;
} }
void mainboard_romstage_entry(void) void mainboard_superio_config(void)
{ {
int s3resume = 0, boot_mode = 0;
enable_lapic();
i82801gx_lpc_setup();
/* Enable SuperIO PM */ /* Enable SuperIO PM */
lpc47m15x_enable_serial(PME_DEV, 0x680); lpc47m15x_enable_serial(PME_DEV, 0x680);
lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : boot_mode, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

59
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -13,20 +13,12 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h> #include <superio/winbond/w83627thg/w83627thg.h>
@ -35,7 +27,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
/* Override the default lpc decode ranges */ /* Override the default lpc decode ranges */
static void mb_lpc_decode(void) void mainboard_lpc_decode(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) if (read_option(lpt, 0) != 0)
@ -49,7 +41,7 @@ static void mb_lpc_decode(void)
* the two. Also set up the GPIOs from the beginning. This is the "no schematic * the two. Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method. * but safe anyways" method.
*/ */
static void early_superio_config_w83627thg(void) void mainboard_superio_config(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;
@ -149,7 +141,7 @@ static void early_superio_config_w83627thg(void)
pnp_exit_conf_state(dev); pnp_exit_conf_state(dev);
} }
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
@ -167,48 +159,3 @@ static void rcba_config(void)
/* Enable PCIe Root Port Clock Gate */ /* Enable PCIe Root Port Clock Gate */
} }
void mainboard_romstage_entry(void)
{
int s3resume = 0;
enable_lapic();
i82801gx_lpc_setup();
mb_lpc_decode();
early_superio_config_w83627thg();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}

92
src/mainboard/lenovo/t60/romstage.c
View File

@ -15,25 +15,18 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <cf9_reset.h>
#include <delay.h> #include <delay.h>
#include <stdint.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include "dock.h" #include "dock.h"
/* Override the default lpc decode ranges */ /* Override the default lpc decode ranges */
static void mb_lpc_decode(void) void mainboard_lpc_decode(void)
{ {
// decode range // decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
@ -55,7 +48,25 @@ static void early_superio_config(void)
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
} }
static void rcba_config(void) void mainboard_superio_config(void)
{
/* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars();
setup_pch_gpios(&mainboard_gpio_map);
int dock_err = dlpc_init();
/* We prefer Legacy I/O module over docking */
if (legacy_io_present()) {
legacy_io_init();
early_superio_config();
} else if (!dock_err && dock_present()) {
dock_connect();
early_superio_config();
}
}
void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
RCBA32(V0CTL) = 0x80000001; RCBA32(V0CTL) = 0x80000001;
@ -86,63 +97,8 @@ static void rcba_config(void)
RCBA64(IOTR3) = 0x000200f0000c0801ULL; RCBA64(IOTR3) = 0x000200f0000c0801ULL;
} }
void mainboard_romstage_entry(void) void mainboard_get_spd_map(u8 spd_map[4])
{ {
int s3resume = 0; spd_map[0] = 0x50;
int dock_err; spd_map[2] = 0x51;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
enable_lapic();
/* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars();
setup_pch_gpios(&mainboard_gpio_map);
i82801gx_lpc_setup();
mb_lpc_decode();
dock_err = dlpc_init();
/* We prefer Legacy I/O module over docking */
if (legacy_io_present()) {
legacy_io_init();
early_superio_config();
} else if (!dock_err && dock_present()) {
dock_connect();
early_superio_config();
}
/* Setup the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

100
src/mainboard/lenovo/x60/romstage.c
View File

@ -15,26 +15,18 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h>
#include <cf9_reset.h>
#include <delay.h> #include <delay.h>
#include <stdint.h>
#include <device/pnp_def.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include "dock.h" #include "dock.h"
/* Override the default lpc decode ranges */ /* Override the default lpc decode ranges */
static void mb_lpc_decode(void) void mainboard_lpc_decode(void)
{ {
// decode range // decode range
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210);
@ -56,7 +48,24 @@ static void early_superio_config(void)
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
} }
static void rcba_config(void) void mainboard_superio_config(void)
{
/* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars();
setup_pch_gpios(&mainboard_gpio_map);
dlpc_init();
/* dock_init initializes the DLPC switch on
* thinpad side, so this is required even
* if we're undocked.
*/
if (dock_present()) {
dock_connect();
early_superio_config();
}
}
void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
RCBA32(V0CTL) = 0x80000001; RCBA32(V0CTL) = 0x80000001;
@ -87,68 +96,9 @@ static void rcba_config(void)
RCBA64(IOTR3) = 0x000200f0000c0801ULL; RCBA64(IOTR3) = 0x000200f0000c0801ULL;
} }
void mainboard_romstage_entry(void)
void mainboard_get_spd_map(u8 spd_map[4])
{ {
int s3resume = 0; spd_map[0] = 0x50;
const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; spd_map[2] = 0x51;
enable_lapic();
/* Set up GPIO's early since it is needed for dock init */
i82801gx_setup_bars();
setup_pch_gpios(&mainboard_gpio_map);
i82801gx_lpc_setup();
mb_lpc_decode();
dlpc_init();
/* dock_init initializes the DLPC switch on
* thinpad side, so this is required even
* if we're undocked.
*/
if (dock_present()) {
dock_connect();
early_superio_config();
}
/* Set up the console */
console_init();
if (dock_present())
printk(BIOS_DEBUG, "Dock is present\n");
else
printk(BIOS_DEBUG, "Dock is not present\n");
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n");
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

56
src/mainboard/roda/rk886ex/romstage.c
View File

@ -20,18 +20,13 @@
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
#include "option_table.h" #include "option_table.h"
/* Override the default lpc decode ranges */ /* Override the default lpc decode ranges */
static void mb_lpc_decode(void) void mainboard_lpc_decode(void)
{ {
int lpt_en = 0; int lpt_en = 0;
if (read_option(lpt, 0) != 0) if (read_option(lpt, 0) != 0)
@ -59,7 +54,7 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
outb(0xaa, port); outb(0xaa, port);
} }
static void early_superio_config(void) void mainboard_superio_config(void)
{ {
pnp_devfn_t dev; pnp_devfn_t dev;
@ -94,7 +89,7 @@ static void early_superio_config(void)
pnp_exit_ext_func_mode(dev); pnp_exit_ext_func_mode(dev);
} }
static void rcba_config(void) void mainboard_late_rcba_config(void)
{ {
/* Set up virtual channel 0 */ /* Set up virtual channel 0 */
@ -129,50 +124,7 @@ static void init_artec_dongle(void)
outb(0xf4, 0x88); outb(0xf4, 0x88);
} }
void mainboard_romstage_entry(void) void mainboard_pre_raminit_config(int s3_resume)
{ {
int s3resume = 0;
enable_lapic();
i82801gx_lpc_setup();
mb_lpc_decode();
early_superio_config();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
/* This has to happen after i945_early_initialization() */
init_artec_dongle(); init_artec_dongle();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
sdram_initialize(s3resume ? 2 : 0, NULL);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
} }

1
src/northbridge/intel/i945/Makefile.inc
View File

@ -20,6 +20,7 @@ ramstage-y += northbridge.c
ramstage-y += gma.c ramstage-y += gma.c
ramstage-y += acpi.c ramstage-y += acpi.c
romstage-y += romstage.c
romstage-y += memmap.c romstage-y += memmap.c
romstage-y += raminit.c romstage-y += raminit.c
romstage-y += early_init.c romstage-y += early_init.c

12
src/northbridge/intel/i945/i945.h
View File

@ -375,6 +375,18 @@ void sdram_dump_mchbar_registers(void);
u32 decode_igd_memory_size(u32 gms); u32 decode_igd_memory_size(u32 gms);
u32 decode_tseg_size(const u8 esmramc); u32 decode_tseg_size(const u8 esmramc);
/* Romstage mainboard callbacks */
/* Optional: Override the default LPC config. */
void mainboard_lpc_decode(void);
/* Optional: Initialize the superio for serial output. */
void mainboard_superio_config(void);
/* Optional: mainboard specific init after console init and before raminit. */
void mainboard_pre_raminit_config(int s3_resume);
/* Mainboard specific RCBA init. Happens after raminit. */
void mainboard_late_rcba_config(void);
/* Optional: mainboard callback to get SPD map */
void mainboard_get_spd_map(u8 spd_map[4]);
#endif /* __ACPI__ */ #endif /* __ACPI__ */
#endif /* NORTHBRIDGE_INTEL_I945_H */ #endif /* NORTHBRIDGE_INTEL_I945_H */

95
src/northbridge/intel/i945/romstage.c Normal file
View File

@ -0,0 +1,95 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cf9_reset.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h>
__weak void mainboard_lpc_decode(void)
{
}
__weak void mainboard_superio_config(void)
{
}
__weak void mainboard_pre_raminit_config(int s3_resume)
{
}
__weak void mainboard_get_spd_map(u8 spd_map[4])
{
spd_map[0] = 0x50;
spd_map[1] = 0x51;
spd_map[2] = 0x52;
spd_map[3] = 0x53;
}
void mainboard_romstage_entry(void)
{
int s3resume = 0;
u8 spd_map[4] = {};
enable_lapic();
i82801gx_lpc_setup();
mainboard_lpc_decode();
mainboard_superio_config();
/* Set up the console */
console_init();
if (MCHBAR16(SSKPD) == 0xCAFE) {
system_reset();
}
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
i82801gx_early_init();
i945_early_initialization();
s3resume = southbridge_detect_s3_resume();
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
mainboard_pre_raminit_config(s3resume);
if (CONFIG(DEBUG_RAM_SETUP))
dump_spd_registers();
mainboard_get_spd_map(spd_map);
sdram_initialize(s3resume ? 2 : 0, spd_map);
/* This should probably go away. Until now it is required
* and mainboard specific
*/
mainboard_late_rcba_config();
/* Chipset Errata! */
fixup_i945_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
}