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soc/amd/cezanne: Enable CBFS_PRELOAD 

The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was
derived by examining the `cbfstool print` output and summing the files
we intend to preload.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Raul E Rangel 2021-11-02 11:51:48 -06:00 committed by Paul Fagerburg
parent cb902fd6bb
commit dcd8114359
1 changed files with 5 additions and 0 deletions
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5
src/soc/amd/cezanne/Kconfig
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@ -195,6 +195,7 @@ config ASYNC_FILE_LOADING
bool "Loads files from SPI asynchronously" bool "Loads files from SPI asynchronously"
select COOP_MULTITASKING select COOP_MULTITASKING
select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
select CBFS_PRELOAD
select PAYLOAD_PRELOAD select PAYLOAD_PRELOAD
help help
When enabled, the platform will use the LPC SPI DMA controller to When enabled, the platform will use the LPC SPI DMA controller to
@ -202,6 +203,10 @@ config ASYNC_FILE_LOADING
boot time because the CPUs can be performing useful work while the boot time because the CPUs can be performing useful work while the
SPI contents are being preloaded. SPI contents are being preloaded.
config CBFS_CACHE_SIZE
hex
default 0x40000 if CBFS_PRELOAD
config RAMBASE config RAMBASE
hex hex
default 0x10000000 default 0x10000000