GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specific 

STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().

BUG=b:116196626
TEST=build and boot grunt

Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel 2018-09-20 14:50:11 -07:00 committed by Martin Roth
parent e072247e6e
commit dd9b1d1dd5
4 changed files with 27 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
View File

@ -149,27 +149,8 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{ {
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
struct _PLATFORM_CONFIGURATION *platform;
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
if (!dev || !dev->chip_info) {
printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
" config, STAPM unchanged\n");
return;
}
cfg = dev->chip_info;
platform = &InitEarly->PlatformConfig;
if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
platform->PlatStapmConfig.CfgStapmTimeConstant =
cfg->stapm_time;
platform->PkgPwrLimitDC = cfg->stapm_power;
platform->PkgPwrLimitAC = cfg->stapm_power;
platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
}
} }

1
src/soc/amd/common/block/include/amdblocks/agesawrapper.h
View File

@ -63,5 +63,6 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params);
void SetFchMidParams(FCH_INTERFACE *params); void SetFchMidParams(FCH_INTERFACE *params);
void SetNbMidParams(GNB_MID_CONFIGURATION *params); void SetNbMidParams(GNB_MID_CONFIGURATION *params);
void set_board_env_params(GNB_ENV_CONFIGURATION *params); void set_board_env_params(GNB_ENV_CONFIGURATION *params);
void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly);
#endif /* __AGESAWRAPPER_H__ */ #endif /* __AGESAWRAPPER_H__ */

3
src/soc/amd/common/block/pi/agesawrapper.c
View File

@ -31,6 +31,8 @@
#include <amdblocks/image.h> #include <amdblocks/image.h>
#include <amdblocks/BiosCallOuts.h> #include <amdblocks/BiosCallOuts.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <soc/northbridge.h>
#include <soc/cpu.h>
void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {} void __weak SetMemParams(AMD_POST_PARAMS *PostParams) {}
void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {} void __weak OemPostParams(AMD_POST_PARAMS *PostParams) {}
@ -129,6 +131,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct); AMD_EARLY_PARAMS *EarlyParams = create_struct(&AmdParamStruct);
soc_customize_init_early(EarlyParams);
OemCustomizeInitEarly(EarlyParams); OemCustomizeInitEarly(EarlyParams);
timestamp_add_now(TS_AGESA_INIT_EARLY_START); timestamp_add_now(TS_AGESA_INIT_EARLY_START);

23
src/soc/amd/stoneyridge/romstage.c
View File

@ -222,3 +222,26 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
break; break;
} }
} }
void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
struct _PLATFORM_CONFIGURATION *platform;
if (!dev || !dev->chip_info) {
printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree"
" config, STAPM unchanged\n");
return;
}
cfg = dev->chip_info;
platform = &InitEarly->PlatformConfig;
if ((cfg->stapm_percent) && (cfg->stapm_time) && (cfg->stapm_power)) {
platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent;
platform->PlatStapmConfig.CfgStapmTimeConstant =
cfg->stapm_time;
platform->PkgPwrLimitDC = cfg->stapm_power;
platform->PkgPwrLimitAC = cfg->stapm_power;
platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled;
}
}