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intel/skylake: Add devicetree setting for DDR frequency limit UPD 

There is a UPD setting exposed by FSP that allows the DDR
frequency to be limited.  Expose this for devicetree.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=tested by limiting DDR frequency to 1600 on chell EVT

Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12981
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Duncan Laurie 2015-12-10 01:01:59 -08:00 committed by Patrick Georgi
parent 63f8c0af4b
commit ddd9f1a5a6
2 changed files with 7 additions and 0 deletions
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6
src/soc/intel/skylake/chip.h
View File

@ -113,6 +113,12 @@ struct soc_intel_skylake_config {
u32 TsegSize; u32 TsegSize;
u16 MmioSize; u16 MmioSize;
/*
* DDR Frequency Limit
* 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
*/
u16 DdrFreqLimit;
/* Probeless Trace function */ /* Probeless Trace function */
u8 ProbelessTrace; u8 ProbelessTrace;

1
src/soc/intel/skylake/romstage/romstage.c
View File

@ -92,6 +92,7 @@ void soc_memory_init_params(struct romstage_params *params,
upd->EnableTraceHub = config->EnableTraceHub; upd->EnableTraceHub = config->EnableTraceHub;
upd->SaGv = config->SaGv; upd->SaGv = config->SaGv;
upd->RMT = config->Rmt; upd->RMT = config->Rmt;
upd->DdrFreqLimit = config->DdrFreqLimit;
} }
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,