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soc/intel/alderlake: Update cpu and pch tracehub modes 

The patch gets the cpu and pch's tracehub mode from the debug area
of the Descriptor Region and updates the respective UPDs.

TEST=Build, verify the tracehub mode values.

Update CPU' and PCH's Trace Hub modes:
	img=coreboot.rom
	printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc
	printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc

Check coreboot logs:
    [DEBUG]  rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
This commit is contained in:
Sridhar Siricilla 2022-04-28 23:34:14 +05:30 committed by Felix Held
parent 8e3787eaf0
commit dddaeed4c1
1 changed files with 10 additions and 0 deletions
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10
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -8,6 +8,7 @@
#include <drivers/wifi/generic/wifi.h>
#include <fsp/fsp_debug_event.h>
#include <fsp/util.h>
#include <intelbasecode/debug_feature.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pcie_rp.h>
#include <option.h>
@ -387,6 +388,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
fill_fspm_params[i](m_cfg, config);
}
static void debug_override_memory_init_params(FSP_M_CONFIG *mupd)
{
debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_alderlake_config *config;
@ -413,6 +419,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
soc_memory_init_params(m_cfg, config);
mainboard_memory_init_params(mupd);
/* Override the memory init params through runtime debug capability */
if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
debug_override_memory_init_params(m_cfg);
}
__weak void mainboard_memory_init_params(FSPM_UPD *memupd)