mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name

From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune

BUG=None
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kevin Chiu 2020-11-19 14:09:47 +08:00 committed by Felix Held
parent 93859e319e
commit de20b28fe4
9 changed files with 34 additions and 34 deletions

View file

@ -21,7 +21,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -34,7 +34,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -47,7 +47,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -60,7 +60,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -73,7 +73,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -86,7 +86,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -21,7 +21,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -34,7 +34,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -47,7 +47,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -60,7 +60,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -73,7 +73,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -86,7 +86,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -64,7 +64,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -77,7 +77,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -90,7 +90,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -103,7 +103,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -116,7 +116,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -129,7 +129,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -64,7 +64,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -77,7 +77,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -90,7 +90,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -103,7 +103,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x6,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -116,7 +116,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -129,7 +129,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x5,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -30,7 +30,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -42,7 +42,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -54,7 +54,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -66,7 +66,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -37,7 +37,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x9,
.tx_vref_tune = 0x9,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -49,7 +49,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0x9,
.tx_vref_tune = 0x9,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -43,7 +43,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -30,7 +30,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
@ -42,7 +42,7 @@ chip soc/amd/picasso
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"

View file

@ -30,7 +30,7 @@ struct __packed usb2_phy_tune {
/* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
uint8_t tx_rise_tune;
/* HS DC Voltage Level Adjustment. Range 0 - 0xF */
uint8_t rx_vref_tune;
uint8_t tx_vref_tune;
/* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
uint8_t tx_hsxv_tune;
/* USB Source Impedance Adjustment. Range 0 - 0x3. */