soc/intel/jasperlake: Revert CdClock setting

Revert CdClock setting and use default value 0xff.

Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.

BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"

Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/google/dedede/variants/bugzzy/overridetree.cb

@@ -2,9 +2,6 @@ chip soc/intel/jasperlake
 	# MIPI display panel
 	register "DdiPortAConfig" = "2" # DdiPortMipiDsi
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	# Enable Acoustic noise mitigation and set slew rate to 1/8
 	# Rest of the parameters are 0 by default.
 	register "AcousticNoiseMitigation" = "1"

src/mainboard/google/dedede/variants/galtic/overridetree.cb

@@ -75,9 +75,6 @@ chip soc/intel/jasperlake
 
 	register "tcc_offset" = "8"     # TCC of 97C
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			# Default DPTF Policy for all Dedede boards if not overridden

src/mainboard/google/dedede/variants/magolor/overridetree.cb

@@ -108,9 +108,6 @@ chip soc/intel/jasperlake
 	register "SlowSlewRate" = "SlewRateFastBy8"
 	register "FastPkgCRampDisable" = "1"
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf

src/mainboard/google/dedede/variants/metaknight/overridetree.cb

@@ -69,9 +69,6 @@ chip soc/intel/jasperlake
 		.tdp_pl2_override = 12,
 	}"
 
-	# Core Display Clock Frequency selection
-	register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
 	device domain 0 on
 		device pci 04.0 on
 			chip drivers/intel/dptf

src/soc/intel/jasperlake/chip.h

@@ -417,8 +417,6 @@ struct soc_intel_jasperlake_config {
 		CD_CLOCK_312_MHZ   = 5,
 		CD_CLOCK_552_MHZ   = 6,
 		CD_CLOCK_556_8_MHZ = 7,
-		CD_CLOCK_648_MHZ   = 8,
-		CD_CLOCK_652_8_MHZ = 9,
 	} cd_clock;
 
 	/*

src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h

@@ -876,7 +876,7 @@ typedef struct {
 
 /** Offset 0x0436 - CdClock Frequency selection
   0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
-  7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default)
+  0xff: 556.8 MHz (Default)
 **/
   UINT8                       CdClock;